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Pull requests: OpenXiangShan/GEM5
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mem-cache: Align cache hint wakeup ordering with responses
bug
Something isn't working
#861
opened May 25, 2026 by
happy-lx
Contributor
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cpu: Add imHist-assisted MGSC IMLI path
do not merge
#851
opened May 7, 2026 by
jensen-yan
Collaborator
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arch-riscv: Add rvv calibration note[skip ci]
#850
opened May 7, 2026 by
jueshiwenli
Collaborator
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cpu-o3: fix the thread that failed to be triggered due to port busy
#848
opened Apr 30, 2026 by
mhnGitHubz
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arch-riscv: Add an assert for vector splitting.
rvv
#840
opened Apr 22, 2026 by
jueshiwenli
Collaborator
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[codex] Enable MBTB VC16 and approximate dense-block interflush
#826
opened Apr 13, 2026 by
jensen-yan
Collaborator
•
Draft
Refs/heads/tage size align repeat index fill align
#824
opened Apr 13, 2026 by
CJ362ff
Contributor
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Tracking legacy resolve train feature performance
do not merge
perf
#823
opened Apr 10, 2026 by
Yakkhini
Collaborator
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cpu,arch-riscv,cpu-o3,bpu: align control-PC semantics, fetch coverage, and owner migration
perf
#805
opened Mar 22, 2026 by
Lingrui98
Contributor
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configs: reduce UARTLite console PIO latency for Xiangshan bare-metal runs
#789
opened Mar 12, 2026 by
jensen-yan
Collaborator
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