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Make cache-generated hint wakeups follow the same ordering assumptions as the response path. Cache::sendHintViaMSHRTargets() used to treat a delayed first target as a reason to delay every later target in the MSHR. That does not match RespPacketQueue::forceOrder, which only preserves order for targets with the same packet address. Compute each hint's base send time from its own critical-word offset and only inherit a later send time from previous hints that matchAddr(). Also schedule BaseCache::SendCustomEvent at Minimum_Pri so a hint event scheduled for the same tick can fire before CPU tick work. This keeps the wakeup signal ahead of the matching timing response in the same cycle instead of letting it slip behind CPU-side processing. Change-Id: I87a79eccf7ee08f90e7b604808ac04ff96cc6880 Tested: scons build/RISCV/gem5.opt --gold-linker -j64
📝 WalkthroughWalkthroughThis PR modifies cache event scheduling in two coordinated ways: lowering the priority of custom cache events in the simulation queue, and refactoring hint-scheduling logic to track and enforce response-queue ordering constraints so later targets cannot be scheduled earlier than already-enqueued hints for the same address. ChangesHint Event Scheduling
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Verify each finding against current code. Fix only still-valid issues, skip the
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Inline comments:
In `@src/mem/cache/base.cc`:
- Around line 105-106: The constructor BaseCache::SendCustomEvent currently uses
Minimum_Pri which runs this hint before all same-tick events; change it to use a
dedicated, narrower priority (e.g., define CacheHint_Pri) that is positioned
only to beat CPU_Tick_Pri but not Debug_Enable_Pri or CPU_Switch_Pri. Replace
Minimum_Pri in the SendCustomEvent initializer with CacheHint_Pri and add the
CacheHint_Pri constant in the event-priority definitions with a value placed
immediately above/before CPU_Tick_Pri (so it wins against CPU_Tick_Pri but does
not preempt Debug_Enable_Pri/CPU_Switch_Pri). Ensure the new constant is
documented where other priority constants are defined.
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📒 Files selected for processing (2)
src/mem/cache/base.ccsrc/mem/cache/cache.cc
Comment on lines
105
to
+106
| BaseCache::SendCustomEvent::SendCustomEvent(BaseCache* cache, PacketPtr pkt, int sig, bool deletePkt) | ||
| : Event(Stat_Event_Pri, AutoDelete), | ||
| : Event(Minimum_Pri, AutoDelete), |
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Don't use Minimum_Pri for cache hints.
Line 106 now makes SendCustomEvent run before every other same-tick event, including Debug_Enable_Pri and CPU_Switch_Pri. The PR only needs hints to beat CPU_Tick_Pri; using the absolute minimum priority widens the ordering change enough to break unrelated event-queue contracts.
Suggested fix
- : Event(Minimum_Pri, AutoDelete),
+ : Event(CPU_Tick_Pri - 1, AutoDelete),🤖 Prompt for AI Agents
Verify each finding against current code. Fix only still-valid issues, skip the
rest with a brief reason, keep changes minimal, and validate.
In `@src/mem/cache/base.cc` around lines 105 - 106, The constructor
BaseCache::SendCustomEvent currently uses Minimum_Pri which runs this hint
before all same-tick events; change it to use a dedicated, narrower priority
(e.g., define CacheHint_Pri) that is positioned only to beat CPU_Tick_Pri but
not Debug_Enable_Pri or CPU_Switch_Pri. Replace Minimum_Pri in the
SendCustomEvent initializer with CacheHint_Pri and add the CacheHint_Pri
constant in the event-priority definitions with a value placed immediately
above/before CPU_Tick_Pri (so it wins against CPU_Tick_Pri but does not preempt
Debug_Enable_Pri/CPU_Switch_Pri). Ensure the new constant is documented where
other priority constants are defined.
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XXtaoo
approved these changes
May 25, 2026
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Make cache-generated hint wakeups follow the same ordering assumptions as the response path.
Cache::sendHintViaMSHRTargets() used to treat a delayed first target as a reason to delay every later target in the MSHR. That does not match RespPacketQueue::forceOrder, which only preserves order for targets with the same packet address. Compute each hint's base send time from its own critical-word offset and only inherit a later send time from previous hints that matchAddr().
Also schedule BaseCache::SendCustomEvent at Minimum_Pri so a hint event scheduled for the same tick can fire before CPU tick work. This keeps the wakeup signal ahead of the matching timing response in the same cycle instead of letting it slip behind CPU-side processing.
Change-Id: I87a79eccf7ee08f90e7b604808ac04ff96cc6880
Tested: scons build/RISCV/gem5.opt --gold-linker -j64
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