[davidharrishmc]

Fixes finding E in #1980. When the first half of a fetch that crosses a cache line or page faulted, the IFU still decided to spill from the faulting fetch's stale bits and ORed in the second half's page fault, so it reported an instruction page fault with xtval at the first half where Sail and ImperasDV report the first half's access fault. The spill is now taken only when the first half fetches cleanly, so a faulting first half is reported alone, and the first-half fault latch added for #1838 is no longer needed.

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[davidharrishmc]

Review notes: the RTL is correct and adds no timing depth (IFUFaultF already gates CacheRWF, so TakeSpillF already sat behind the PMA/PMP fault path). One gap:

• No test fails without the fix. The bug reproduced only with the FORCE ELF. spillfault.S covers "first half faults, second half clean", which guards the removed latch but not this bug (first half an access fault, second half a page fault; expected cause 1 with xtval = PC). A deterministic case fits in spillfault.S: a PMP no-execute grain on the last halfword of page A, with page B non-executable. Expect mcause 1 and mtval = A+0xFFE; main reports 12.
• Maintainability: correctness for a first-half walk fault relies on the ITLBMissOrUpdateAF port being wired to ITLBMissOrUpdateRawF (ifu.sv:167). Renaming the port, or adding a ~ITLBWalkFaultF term, would make the new comment's invariant ("the spill is not taken if it faults") explicit.

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[davidharrishmc]

Merge order: pairs with #1968 (IFU fetch-buffer reset; merge both) and with #1986, the LSU counterpart (no spill on a first-half fault). The three merge cleanly together.

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[davidharrishmc]

Addressed the review notes:

• Directed test. New tests/coverage/spillbothhalvesfault.S fetches a 32-bit instruction whose first half is in a PMP no-execute grain at the end of page A and whose second half is on a non-executable page B, after a warm-up pass that puts the line in the I$. It expects one instruction access fault with mepc = mtval = the first half and no page fault. On main it fails: Wally reports mcause 12 where ImperasDV reports 1. With this PR it passes on Questa, Verilator and in lockstep.
• Invariant made explicit. The spill port ITLBMissOrUpdateAF is renamed ITLBMissOrUpdateRawF, with comments in spill.sv. The port must carry the miss before masking by a walk fault, because that is what stops a faulting first-half walk from taking the spill: walk faults are not in InstrPageFaultF/InstrAccessFaultF. wave.do follows the rename.
• Merged main.

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