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Comment every module port consistently - #1955

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davidharrishmc wants to merge 15 commits into
openhwfoundation:mainfrom
davidharrishmc:dh/port-comments
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davidharrishmc wants to merge 15 commits into
openhwfoundation:mainfrom
davidharrishmc:dh/port-comments

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@davidharrishmc

@davidharrishmc davidharrishmc commented Oct 10, 2026 •

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Builds on #1952; review only the last commit until that merges.

  • Adds a definition comment to every port in src/ that had none, except clk and reset, which are left uncommented.
  • Rewrites 953 existing comments so the same signal is described the same way everywhere (stage families share a template, e.g. "Stall Decode stage"), and fixes several that were wrong (e.g. LSUFlushW, SelAdrData, IEUAdrExtM).
  • Keeps module-specific text only where a name genuinely means something different (e.g. A/D in the SRAM macros vs. the FPU, Y in generic blocks).

Comments and whitespace only: code tokens are identical to the base, coverage-exclusion GetLineNum targets still match, and lint-wally passes.

🤖 Generated with Claude Code

davidharrishmc and others added 3 commits October 10, 2026 06:19
Fix spelling, grammar, and wrong or garbled comments; normalize
indentation and operator spacing; and add short comments explaining
hard-to-follow control-bit logic, especially in the FPU. Code tokens
are unchanged. Delete eight modules that are never instantiated.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
…dh/sv-cosmetics

Resolve the src/cache/cache.sv conflict by taking openhwfoundation#1948's code (OFFSETLEN
and SETLEN as parameters, NextSet sized OFFSETLEN+SETLEN) and keeping this
branch's comment/whitespace cleanup.  The NextSet comment no longer says
"lower 12 bits", and the new localparams openhwfoundation#1948 added to ifu.sv and lsu.sv
get aligned comments.  After stripping comments and whitespace, every src/
file still matches main.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
Restore fdivsqrtuslc4, prioritythermometer, ram2p1r1wbe_128x64 and
ram2p1r1wbe_2048x64 as they are on main, and put the two RAMs back in
run_vcs's list of memories generated per FPGA target.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
Revert capitalization-only, punctuation-only, and no-gain rewording
edits, restore contributors' informal notes, and keep commented-out code
such as the rom1p1r bootloader initialization and the RAM preload
blocks. Spelling fixes, corrections to wrong comments, added explanatory
comments, and whitespace consistency stay.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
davidharrishmc and others added 3 commits October 10, 2026 07:48
Keep alternate designs, the ROM bootloader initialization, and
optimization notes; drop superseded one-liners, dead predictor flops,
and blocks that reference signals that no longer exist.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Add a definition comment to the 1,430 ports that lacked one and make
comments for the same signal consistent across modules, keeping a
module-specific comment only where the name means something different.

Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply@anthropic.com>
davidharrishmc and others added 3 commits October 15, 2026 15:34
Conflicts were main's logic changes in lines this branch re-indented or
re-commented; each keeps main's code with this branch's formatting:
- fdivsqrtfsm.sv, div.sv: FlushE & ~StallM (openhwfoundation#1925) and its comment; the
  fdivsqrtfsm DONE-state exclusion tag stays removed
- controller.sv: sfence.inval.ir refetch (openhwfoundation#1929)
- tlbcamline.sv: TLBWrite/WritePTE_G/WritePTE_NAPOT ports (openhwfoundation#1927)
- tlbcontrol.sv: ~UpperBitsUnequal in TLBMiss (openhwfoundation#1928), new BadNAPOT comment
- csrc.sv: time/timeh read only with Zicntr (openhwfoundation#1951)

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
Comment the ports main added: hptw ENVCFG_PBMTE, and TLBWrite,
WritePTE_G and WritePTE_NAPOT in tlbcam and tlbcamline (one per line).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
# Conflicts:
#	src/hazard/hazard.sv
#	src/privileged/csr.sv
#	src/privileged/privdec.sv
@davidharrishmc

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Merge order: this is part of the cosmetic stack, merged strictly #1952 → #1955 → #1959 so each delta shows on its own. Merge the open bug-fix PRs first: #1949, #1958, #1967, #1969, #1972, #1982, #1986 and #1987. The stack conflicts textually with them, and re-applying formatting is easier than re-applying fixes.

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davidharrishmc and others added 5 commits October 16, 2026 03:35
# Conflicts:
#	src/hazard/hazard.sv
#	src/mmu/hptw.sv
#	src/privileged/csr.sv
#	src/privileged/csrc.sv
#	src/privileged/privdec.sv
#	src/privileged/privileged.sv
#	src/privileged/trap.sv
LSUHREADY = HREADY & ~LSUDisable, and the arbiter sets LSUDisable while the
IFU holds the bus, so the port comment saying it is never gated was wrong.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>

# Conflicts:
#	src/fpu/fctrl.sv
#	src/fpu/postproc/fmashiftcalc.sv
#	src/fpu/postproc/postprocess.sv
#	src/ifu/bpred/RASPredictor.sv
#	src/ifu/bpred/bpred.sv
#	src/ifu/bpred/icpred.sv
#	src/ifu/ifu.sv
#	src/ifu/spill.sv
#	src/lsu/align.sv
#	src/lsu/lsu.sv
#	src/privileged/csrm.sv
#	src/uncore/uartPC16550D.sv
Signed-off-by: David Harris <David_Harris@hmc.edu>

# Conflicts:
#	src/generic/mem/ram2p1r1wbe_2048x64.sv
#	src/ifu/bpred/RASPredictor.sv
#	src/ifu/bpred/icpred.sv
#	src/ifu/spill.sv
#	src/lsu/align.sv
#	src/mmu/pmachecker.sv
As the PR description says, ports that declare only clk and/or reset carry
no comment; lines that also declare other ports keep theirs.

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
Signed-off-by: David Harris <David_Harris@hmc.edu>
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