Initial ESP32-P4 support by pmnxis · Pull Request #5400 · esp-rs/esp-hal

pmnxis · 2026-04-20T16:39:03Z

ESP32-P4X support on top of esp-hal 1.1.0-rc.0

Submission Checklist

Examples updated or added.
- Not in scope. Test programs live in a separate public repo: https://github.com/pmnxis/esp32p4-hal-testing. See Testing.
  Current the esp32p4-hal-testing repo is link local path pmnxis/esp-hal, but this will be fixed after merge
cargo xtask fmt-packages run.
- Re-run against this branch on the final cleanup pass. P4-only files (psram/esp32p4.rs, rtc_cntl/{rtc,sleep}/esp32p4.rs, soc/esp32p4/{clocks,gpio}.rs) reformatted; firmware still builds cleanly after.
CHANGELOG.md updated.
Migration Guide updated.
- cannot sure it's applicable. Changes are either new P4 code or #[cfg(esp32p4)].
Developer guidelines followed.
- I didn't fixed all lint, because the code I didn't fixed got lint issue after incoming P4, this should be touched in later PR
CONTRIBUTING.md read.

Description

This branch adds early ESP32-P4X support to esp-hal.

ESP32-P4X is Espressif's product name for ESP32-P4 with chip revision v3.1 or later. My board is v3.2 / ECO7, which is an ESP32-P4X.

The branch started from the P4 import in florianL21/esp-hal and was re-applied on top of upstream 1.1.0-rc.0.

Most important change: Zcmp workaround in `esp-sync`

On esp32p4, SingleCoreInterruptLock now matches the ESP-IDF (latest master) workaround for the Zcmp hardware bug (ESP-IDF c27c33a83,
IDF-14279 / DIG-661):

On enter: set mintthresh (CSR 0x347) to 0xff before clearing mstatus.mie. Save the old value.
On exit: re-enable mstatus.mie first, then restore mintthresh.

Without this, some multi-cycle RV32 instruction sequences (for example cm.push) can still be interrupted with mie = 0 and corrupt state.

The change is behind #[cfg(esp32p4)].

Note: on riscv32imafc-unknown-none-elf (our only P4 target) rustc emits zero Zcmp instructions today, so the workaround is defensive -- protecting code paths that current rustc + target combination cannot actually emit, but matching ESP-IDF semantics if a future toolchain enables Zcmp.

Other changes (all esp32p4-only)

ld/esp32p4/memory.x: RAM ends at 0x4FFAE000. The top 72 KB of L2MEM is reserved by the ROM on v3.x silicon.
esp-metadata-generated + esp-metadata/devices/esp32p4.toml: regenerated, added [device.psram] extmem_origin = 0x48000000.
interrupt/riscv/clic.rs: P4 uses a merged int_ctrl register (int_attr_shv + int_attr_trig in one word). Run-level mapping
goes through mintthresh.
soc/esp32p4/clocks.rs, rtc_cntl/rtc/esp32p4.rs, rtc_cntl/sleep/esp32p4.rs: CPLL / SPLL / MPLL bring-up to match
ESP-IDF's clk_tree_ll.c.
New psram/esp32p4.rs (~475 lines): AP HEX-mode PSRAM driver, ported from esp_psram_impl_ap_hex.c. Not yet tested on real PSRAM. init_psram returns true optimistically.
New soc/esp32p4/gpio.rs (~138 lines): LP GPIO RtcPin for GPIO0-5 + GPIO12-23. P4's LP_IO_MUX uses named pinN / padN instead of indexed pin(n) / pad(n).
Small PAC-name fixes in SPI, I2C, UART, GPIO.

Related crates (esp-backtrace, esp-bootloader-esp-idf, esp-println, esp-rom-sys, esp-sync) get esp32p4 feature entries.

Testing

EV Kit	Wiring

Board: ESP32-P4X Function EV Board V1.6, silicon v3.2 / ECO7.

Setup:

ESP-PROG on its 6-pin PROG port, wired to the BOOT / RESET
button nets (UART + DTR/RTS → EN/IO0 auto-reset).
openocd-esp32 v0.12.0 over the chip's USB-Serial/JTAG.

I keep 28 test firmwares in a separate public repo: https://github.com/pmnxis/esp32p4-hal-testing.
A shell harness builds and flashes each one via esptool with USB-native CDC auto-reset. Expected output is recorded in TEST_OUTPUTS.md. Pass/fail shown in the console log and GPIO with logic analyzer.

Peripheral status on ESP32-P4X

Legend:

✅ implemented + hardware-tested
🟡 implemented, partial or unstable test
⚪ implemented, not yet hardware-tested
🚧 stub or not implemented here

Peripheral	Status	Implemented in	Test binary
Boot + `esp_hal::init`	✅	`esp-hal/src/lib.rs`	`test_init`
Chip ID / eFuse	✅	`esp-hal/src/efuse/esp32p4/`	`test_chip_id`, `test_efuse`
Clock tree (CPLL/SPLL/MPLL)	✅	`esp-hal/src/soc/esp32p4/clocks.rs` + `rtc_cntl/rtc/esp32p4.rs`	`test_clock`, `test_clock_switch`
SYSTIMER	✅	existing esp-hal path (P4 metadata now wired)	`test_systimer_corner`
Watchdog disable	✅	existing esp-hal path	`test_wdt`
HP GPIO	✅	existing esp-hal path	`test_gpio`, `test_gpio_all_pins`
LP GPIO (`RtcPin`)	⚪	new `esp-hal/src/soc/esp32p4/gpio.rs`	covered in `test_gpio_all_pins`
UART	✅	`esp-hal/src/uart/mod.rs` (P4 PAC-name fixes)	`test_uart1_wire_w_logicpro` (Logic Pro -verified bit-bang reference). Note: legacy `test_uart_loopback` uses hand-rolled register access with a known GPIO matrix output-enable bug (pre-existing, not driver-related).
I2C master	✅	`esp-hal/src/i2c/master/mod.rs` (P4 `txfifo_start_addr` MMIO fix)	`test_i2c_wire_w_logicpro` (LA-verified), `test_i2c_scan` (driver-instantiation smoke test)
SPI master	⚪	`esp-hal/src/spi/master/mod.rs` (P4 `cmd.update()` fix)	none yet
GDMA (mem2mem)	✅	`esp-hal/src/dma/gdma/*`	`test_dma_mem2mem`, `test_sram_psram_crossover`
AES / SHA / RSA	🟡	existing esp-hal path (P4 metadata)	`test_crypto`, `test_crypto_rng_dma`
CLIC + interrupts	✅	`esp-hal/src/interrupt/riscv/clic.rs`	`test_interrupt`
Memory bounds / PMP	🟡	application-level (`pmp_init.rs` in firmware, not esp-hal)	`test_memory_boundary`
PSRAM (HEX mode)	🚧	new `esp-hal/src/psram/esp32p4.rs` stub	`test_psram` failed in current testing code. Need more studying with proffer PMP configuration
EMAC (100M RMII)	🟡	downstream firmware driver (not in this PR)	`test_emac_phy` — MDIO OK (IDR1=0x0243). EMAC MAC driver itself is out of scope for this PR.
USB OTG HS (DWC2)	🟡	downstream firmware driver (not in this PR)	`test_usb_dwc2`, `test_usb_raw`
USB Serial/JTAG	✅	existing esp-hal path	used for all test console output
Errata MSPI-749/750/751, APM-560, DMA-767	⚪	application-level workarounds (out of scope for this PR)	`test_errata*` (passes where documented)
Zcmp critical-section	✅	this PR `esp-sync/src/raw.rs`	defensive (rustc emits zero Zcmp on `riscv32imafc`); verified the surrounding lock semantics still pass `test_init`, `test_i2c_scan`, embassy-net Runner spawn, MDIO read

Known open items (NOT fixed by this PR)

TODO -- to be addressed in follow-up PRs:

rtc_cntl/sleep/esp32p4.rs -- sleep mode + PMU wakeup state machine (stub).
rtc_cntl/rtc/esp32p4.rs -- wakeup-source enumeration, several PMU paths.
soc/esp32p4/clocks.rs -- APB divider write, UART/TIMG clock source mux, mux/source enable stubs.
psram/esp32p4.rs -- ECC enable; init_psram currently optimistic.
LP Related
EMAC MAC driver -- out of scope; MDIO read works but need more testing (IP101GRI PHY 0x0243).
HIL test integration (hil-test/Cargo.toml + hil.yml matrix) -- needs per-bin #[cfg(not(esp32p4))] gating.
PAC drift: i2c/spi/clic.rs/clock/rtc_cntl shims carry inline TODOs to file esp-pacs PRs and collapse the cfg branches.
HP_SYS_CLKRST.CPU_WAITI_CTRL0 -- raw MMIO, TODO for PAC accessor.
DMA naming reconciliation (pac::ahb_dma as gdma_pac alias).
regi2c -- low-level regi2c_read/regi2c_write + regi2c_enable_block are in place (matches PR Enable regi2c-related clocks in regi2c enable_block impls #5405, fixes C6 (v0.0) deep sleep stuck on RtcClock::calibrate #5366). define_regi2c! macros for P4 analog registers (CPLL/SPLL/MPLL/BBPLL/LDO) are not yet ported -- needed before any driver wants typed access to PLL/bias trims. Tracking under the umbrella of issue QOL: Do something about regi2c_* functions. #1740.
Semver-Check baseline -- no prior baseline (first re-introduction since Remove partial support for the ESP32-P4 #1461); skip-semver-checks label requested, auto-seeds post-merge.

Cherry-picked new files only (no conflicting modifications) from florianL21's esp32p4-support branch (commit 606f006). Includes: - Linker scripts (esp32p4.x, memory.x, linkall.x) - eFuse field definitions - RTC control and sleep mode support - SoC clock definitions and regi2c - Generated metadata for esp32p4 - ROM linker scripts (including eco5/P4X variants) - Radio clocks low-level (relocated to esp-radio/) These files need verification against ESP32-P4X (chip rev v3.1+) datasheet and TRM. P4X has significant silicon differences from earlier P4 revisions (eco4/NRND). Based on work by FlorianL21 <6053565+florianL21@users.noreply.github.com>

- Add esp32p4 PAC dependency (v0.2, from esp-pacs at fc3e6d4) - Add esp32p4 feature with CLIC-48, LP core, RTC RAM support (matching esp32c5/c61 pattern for RISC-V CLIC chips) - Update memory.x linker script: - Conservative RAM origin at 0x4FF40000 (avoids ROM reserved 256 KB) - Verified against esp-idf SOC_IRAM_LOW/HIGH, SOC_DIRAM_ROM_RESERVE_HIGH - Note L2MEM cached region change in v3.x (bottom-up vs top-down) - Add rt feature forwarding for esp32p4 PAC Target: ESP32-P4NRW16X / ESP32-P4NRW32X (chip revision v3.0/v3.1) NOT for NRND variants (ESP32-P4NRW32 without X suffix). References: - TRM v0.5 (Pre-release), Table 1.4-1 CPU Address Map - Datasheet v0.5, Table 1-1 Series Comparison - Chip Revision v3.x User Guide v1.0 (2026.03) - esp-idf components/soc/esp32p4/include/soc/soc.h

- Linker scripts (ld/esp32p4/*): RAM ends at 0x4FFAE000 per v3.x ROM reserve. - Regen esp-metadata(-generated) for esp32p4: SoC capability flags consistent. - CLIC / interrupt layer: consolidated int_ctrl regs; mintthresh run-level. - Clock tree (src/soc/esp32p4 + rtc_cntl): CPLL/SPLL/MPLL aligned to esp-idf. - New: src/psram/esp32p4.rs (AP HEX mode) and src/soc/esp32p4/gpio.rs (LP GPIO). - esp-sync/raw.rs: RV32 Zcmp hardware-bug workaround (mintthresh=0xff bracket around critical sections), mirrors esp-idf commit c27c33a83. #[cfg(esp32p4)]. - Misc PAC-name compat + xtask clippy auto-fix. Validated on P4X EV Board V1.7, silicon v3.2/ECO7: esp_hal::init -> embassy-net Runner -> IP101GRI MDIO alive.

Pulls in esp-hal 1.1.0-rc.0 release + 29 upstream commits. Conflict resolutions (P4 branch stance preserved): - esp-hal/Cargo.toml, esp-rom-sys/Cargo.toml: take upstream's bumped published PAC versions for all chips, keep esp32p4 = 0.2 pinned to git rev fc3e6d4 (required for our regenerated PAC layout). - esp-hal/README.md: keep HEAD (has ESP32-P4 column); machine-gen table will be refreshed by xtask on next regen. - xtask/src/commands/release/bump_version.rs: take upstream's rename `bump_version_number` -> `bump_base`. - esp-metadata + _generated_esp32p4.rs: add [device.psram] extmem_origin = 0x48000000 (required by upstream's new `property!("psram.extmem_origin")` use in esp-hal/src/psram/mod.rs). - esp-hal/src/psram/esp32p4.rs: adapt init_psram signature to upstream's post-merge API `(&mut PsramConfig) -> bool` + add map_psram stub returning the vaddr range; underlying HEX-mode impl unchanged. Validated: firmware builds, boots, EMAC/PHY init still reaches `PHY diag: scan addr=1 IDR1=0x0243 IDR2=0x0C54 (alive)`.

bugadani · 2026-04-20T17:55:39Z

Please don't change the release tooling in a PR that's not meant to do that

pmnxis · 2026-04-20T18:02:02Z

Please don't change the release tooling in a PR that's not meant to do that

@bugadani Oops I touched it while just run "cargo clippy --fix" I will revert them.
Thanks for let me know

bugadani · 2026-04-21T08:02:31Z

+   Each maps to DefaultHandler unless overridden by the application.
+   Ref: esp32p4 PAC lib.rs __EXTERNAL_INTERRUPTS vector table
+        TRM v0.5 Ch 14 (Interrupt Matrix) */
+PROVIDE(LP_WDT = DefaultHandler);


Peripheral interrupt symbols are provided by the PAC (https://github.com/esp-rs/esp-pacs/blob/main/esp32p4/device.x), and the PAC's device.x is included by hal-defaults.x. These shouldn't be listed in esp-hal.

Removed and confirmed it still builds.
I originally added these because I wasn't sure the PAC exposed the full interrupts, and I was worried different v3.x silicon revisions might expose different tables. (because very few information about 3.2 that I have)
Neither turned out to be true, PAC's device.x covers all 99 entries and they are the same across v3.x.
Thanks!

bugadani · 2026-04-21T08:04:08Z

+                // P4 PAC: intr_0() (Core0 GPIO interrupt status)
+                // Ref: esp-idf gpio_ll.h -- gpio_ll_get_intr_status()
+                //      TRM v0.5 Ch 11 -- GPIO_STATUS_INT_REG


This is some LLM output, right? There's absolutely no need to cross-reference either esp-idf source code, or the TRM for these sorts of simple, obvious pieces of code.

@bugadani Yes, assisted while TRM indexing.
But ESP-IDF and TRM citations were my decision.
v3.2 silicon info it not clear when I've got and it's unclear which tracks late-revision adopt faster.
So I cited both defensively.
But you're right that for trivial register reads it's noise. It's still draft PR and need to be remove that when I think it's enough to reference esp-idf side.

Some of memory offset and address is not shown in TRM.
In this case, I keep left some idf based header/source name on comment.

bugadani · 2026-04-21T08:14:39Z

+            // P4 uses dedicated pins (GPIO49/50) for USB, so USB_DM/USB_DP are
+            // not in the analog function table -> this inner fn is unused on P4.


This should clearly say "pins 49 and 50", not GPIO49 and GPIO50. These are not GPIOs, but dedicated pins. But this is only true for USB HS, and not to USB Serial/JTAG or USB FS, which have their own DM and DP signals in the analog function table.

// TODO: considering USB1P1_N0/1 USB1P1_P0/1 on P4 // On P4 the analog table uses USB_PHY{0,1}_DM/DP instead of // USB_DM/DP, so neither arm below matches and this fn is unused.

fixed like this

bugadani · 2026-04-21T08:18:12Z

+        } else if #[cfg(esp32p4)] {
+            // P4: CPU_WAITI_CTRL0_REG in HP_SYS_CLKRST (offset 0xf4) controls
+            // whether WFI gates the clock. Default: core0_waiti_icg_en=1 (enabled).
+            // This register is only in hw_ver3 (eco5+), not in current PAC.
+            // Ref: esp-idf hp_sys_clkrst_reg.h -- HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG
+            //      TRM v0.5 Ch 22 (v3.x addition)
+            // Return true (WFI clock gating active) -- matches default hardware state.
+            true


We only intend to support hw_ver3. If this register is not in the current PAC, it should be added. At least mark this place with a TODO label, please.

4381c33
improved this. But need review again.
I am not sure what's right aporach between reading per bit or just judge 0th bit .

github-actions · 2026-04-24T14:49:01Z

New commits in main has made this PR unmergable. Please resolve the conflicts.

github-actions · 2026-04-27T10:28:58Z

New commits in main has made this PR unmergable. Please resolve the conflicts.

bugadani · 2026-04-29T15:34:59Z

What can we do to help you get this into a mergeable state? This PR is huge, so it will just accumulate merge conflicts in its current state. It's not necessary to enable everything all at once, we've added support for other chips incrementally recently.

pmnxis · 2026-05-04T05:21:15Z

~~For now, I am looking for bump-up p4 esp-pacs to 788901b.~~
esp-rs/esp-pacs#425
But not sure about applying it in this PR.

This work will be belong to future PR or others' turn

bugadani · 2026-05-04T06:36:16Z

@@ -1,38 +1,82 @@
+// ESP32P4 follows pulp CLIC version 1.x


This file will either need to be split into two, or the naming should be updated in the PAC to be consistent.

But I dont sure about splitting, because there's some possibility ESP32P4 upgrade their CLIC or future pac takes compatibility with 2.x stuff.

This is more a note to ourselves, I think you've done quite enough here already :) Also I hope the hardware won't change drastically once more.

me either, I don't wanna espressif change it.
I will make issues on esp-pacs about this and left more comment on the code

reason of keep v1.x and v2.x

what to do on future , split or keep by future action

// CLIC v1.x and v2.x currently coexist in this file. Depending on // ESP32-P4 mass production results and future esp-rs/esp-pacs patches, // this file may be split into clic_v1.rs / clic_v2.rs, or kept as is. // // TODO: keep tracking future P4 revision to check changes of CLIC. // // ESP32P4 follows pulp CLIC version 1.x

pmnxis · 2026-05-04T08:06:38Z

- ESP32-C Series: _ESP32-C2, ESP32-C3, ESP32-C6_
+- ESP32-C Series: _ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61_
 - ESP32-H Series: _ESP32-H2_
+- ESP32-P Series: _ESP32-P4_


Maybe this is out of scope. But touched.
Because when I look on the code and add P4 here, looks like C5/C61 is already supported in esp-hal

pmnxis · 2026-05-04T08:16:27Z

+MEMORY
+{
+    /* CONFIG 0 */
+#IF ESP_HAL_CONFIG_L2_CACHE_SIZE_512KB
+    RAM : ORIGIN = 0x4FF80000, LENGTH = 0x4FFAE000 - 0x4FF80000
+#ENDIF
+    /* CONFIG 1 */
+#IF ESP_HAL_CONFIG_L2_CACHE_SIZE_256KB
+    RAM : ORIGIN = 0x4FF40000, LENGTH = 0x4FFAE000 - 0x4FF40000
+#ENDIF
+    /* CONFIG 2 */
+#IF ESP_HAL_CONFIG_L2_CACHE_SIZE_128KB
+    RAM : ORIGIN = 0x4FF20000, LENGTH = 0x4FFAE000 - 0x4FF20000
+#ENDIF
+    /* CONFIG 3 */
+#IF ESP_HAL_CONFIG_L2_CACHE_SIZE_0KB


CONFIG 0:3 naming were came from TRM.

pmnxis · 2026-05-04T14:46:12Z

Synced with main (which brought in #5519)

bugadani

Thank you very much for getting the chip this far! There is quite a bit still missing - basics like esp-alloc or esp-rtos don't work, probe-rs has difficulties flashing the chip, so tests don't boot, and the code is not really consistent with the repository, but this is still a very good first step!

pmnxis added 5 commits April 13, 2026 01:38

Reformat with cargo xtask fmt-packages

35b3f78

bugadani reviewed Apr 20, 2026

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Comment thread esp-hal/src/clock/mod.rs Outdated

bugadani reviewed Apr 20, 2026

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Comment thread esp-hal/src/dma/gdma/ahb_v2.rs Outdated

bugadani reviewed Apr 21, 2026

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pmnxis added 5 commits April 22, 2026 02:05

Revert modification tooling of esp-hal by clippy

b9d606d

Addressing comment avoid DW DMA

0250e7a

Remove redundant interrupt provides from esp32p4.x PAC

b1545b0

Addressing comment USB and wrong metadata P4

6a788e9

P4 cpu_wait_mode_on, per-core WAITI_ICG_EN read.

4381c33

bugadani mentioned this pull request Apr 23, 2026

Initial P4 support tracking issue #2285

Open

5 tasks

github-actions Bot added the merge-conflict Merge conflict detected. Automatically added/removed by CI. label Apr 24, 2026

pmnxis added 2 commits April 27, 2026 01:16

Remove some reference tracking comment (p4)

e68b4ac

Tyding to latest esp-hal (b2905c3)

aa9c0dd

github-actions Bot removed the merge-conflict Merge conflict detected. Automatically added/removed by CI. label Apr 26, 2026

pmnxis changed the title ~~ESP32-P4X support on top of esp-hal 1.1.0-rc.0~~ ESP32-P4X support on top of esp-hal 1.1.0 Apr 27, 2026

github-actions Bot added the merge-conflict Merge conflict detected. Automatically added/removed by CI. label Apr 27, 2026

bugadani reviewed Apr 27, 2026

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Comment thread esp-bootloader-esp-idf/src/lib.rs Outdated

Addressing comment about crc and md5 rom

b0b003d

Lint for P4X, but not fix them all

a8c86ee

pmnxis marked this pull request as ready for review May 3, 2026 19:36

pmnxis commented May 3, 2026

View reviewed changes

Comment thread esp-hal/src/psram/esp32p4.rs

Add better comment on clic.rs

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pmnxis commented May 4, 2026

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Comment thread esp-hal/src/interrupt/riscv/clic.rs Outdated

bugadani reviewed May 4, 2026

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bugadani changed the title ~~ESP32-P4X support on top of esp-hal 1.1.0~~ Initial ESP32-P4 support May 4, 2026

pmnxis commented May 4, 2026

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Delete p4 radio clk and fix right l2mem cfg comment

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pmnxis commented May 4, 2026

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pmnxis and others added 4 commits May 4, 2026 17:39

Important note about clic.rs

1b91a7e

Merge branch 'main' into pmnxis/esp32p4x

11c6c5d

Tyding to latest esp-rs#5473

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Merge branch 'esp-rs:main' into pmnxis/esp32p4x

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pmnxis mentioned this pull request May 4, 2026

Skip baseline check if chip-specific baseline is not found #5519

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Apply ChangeLog considering cicd

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pmnxis force-pushed the pmnxis/esp32p4x branch from ac9e7f3 to 23adb5d Compare May 4, 2026 13:15

Consider fmt-packages for P4

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bugadani mentioned this pull request May 4, 2026

Unify differences of I2S hardware via metadata, add C5 and C61 I2S support #5483

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Merge branch 'main' into pmnxis/esp32p4x

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bugadani added 2 commits May 4, 2026 18:55

Fix esp-println and enable the hello_world examples

7030d87

Enable the GPIO example

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bugadani approved these changes May 4, 2026

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Merge branch 'main' into pmnxis/esp32p4x

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bugadani added this pull request to the merge queue May 5, 2026

Merged via the queue into esp-rs:main with commit 2ccf50d May 5, 2026
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Copilot AI mentioned this pull request May 5, 2026

P4: update PAC, enable some basics #5523

Open

		// P4 uses dedicated pins (GPIO49/50) for USB, so USB_DM/USB_DP are
		// not in the analog function table -> this inner fn is unused on P4.

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Submission Checklist

Description

Most important change: Zcmp workaround in esp-sync

Other changes (all esp32p4-only)

Testing

Peripheral status on ESP32-P4X

Known open items (NOT fixed by this PR)

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pmnxis commented Apr 20, 2026 •

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Most important change: Zcmp workaround in `esp-sync`

pmnxis commented Apr 20, 2026 •

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pmnxis commented May 4, 2026 •

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