Initial ESP32-P4 support

README.md

@@ -16,8 +16,9 @@
 Bare-metal (`no_std`) hardware abstraction layer for Espressif devices. Currently supports the following devices:
 
 - ESP32 Series: _ESP32_
-- ESP32-C Series: _ESP32-C2, ESP32-C3, ESP32-C6_
+- ESP32-C Series: _ESP32-C2, ESP32-C3, ESP32-C5, ESP32-C6, ESP32-C61_
 - ESP32-H Series: _ESP32-H2_
+- ESP32-P Series: _ESP32-P4_
 - ESP32-S Series: _ESP32-S2, ESP32-S3_
 
 Additionally provides support for programming the low-power RISC-V cores found on the _ESP32-C6_, _ESP32-S2_, and _ESP32-S3_ via the [esp-lp-hal] package.

esp-backtrace/CHANGELOG.md

@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Added
 
+- Initial ESP32-P4 (chip revision v3.0+) support (#5400)
 
 ### Changed
 

esp-backtrace/Cargo.toml

@@ -61,6 +61,7 @@ esp32c5 = ["esp-println?/esp32c5", "esp-metadata-generated/esp32c5"]
 esp32c6 = ["esp-println?/esp32c6", "esp-metadata-generated/esp32c6"]
 esp32c61 = ["esp-println?/esp32c61", "esp-metadata-generated/esp32c61"]
 esp32h2 = ["esp-println?/esp32h2", "esp-metadata-generated/esp32h2"]
+esp32p4 = ["esp-println?/esp32p4", "esp-metadata-generated/esp32p4"]
 esp32s2 = ["esp-println?/esp32s2", "esp-metadata-generated/esp32s2", "semihosting?/openocd-semihosting"]
 esp32s3 = ["esp-println?/esp32s3", "esp-metadata-generated/esp32s3", "semihosting?/openocd-semihosting", "print-float-registers"]
 

esp-bootloader-esp-idf/CHANGELOG.md

@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Changed
 
+- ESP32-P4: Use ROM CRC32 / MD5 functions instead of the software fallback (#5400)
 
 ### Fixed
 

esp-bootloader-esp-idf/Cargo.toml

@@ -83,6 +83,8 @@ esp32c61   = ["esp-rom-sys/esp32c61", "esp-metadata-generated/esp32c61", "esp-ha
 ##
 esp32h2   = ["esp-rom-sys/esp32h2", "esp-metadata-generated/esp32h2", "esp-hal/esp32h2"]
 ##
+esp32p4   = ["esp-rom-sys/esp32p4", "esp-metadata-generated/esp32p4", "esp-hal/esp32p4"]
+##
 esp32     = ["esp-rom-sys/esp32", "esp-metadata-generated/esp32", "esp-hal/esp32"]
 ##
 esp32s2   = ["esp-rom-sys/esp32s2", "esp-metadata-generated/esp32s2", "esp-hal/esp32s2"]

esp-bootloader-esp-idf/src/partitions.rs

@@ -336,6 +336,13 @@ impl<'a> PartitionTable<'a> {
                 let paddr = unsafe {
                     ((0x600c5000 as *const u32).read_volatile() & 0xff) << 16
                 };
+            } else if #[cfg(feature = "esp32p4")] {
+                // DR_REG_FLASH_SPI0_BASE : 0x5008C000 = DR_REG_HPPERIPH0_BASE + 0x8C000
+                // TODO: verify MSPI register for partition physical address read
+                let paddr = unsafe {
+                    ((0x5008C000 + 0x380) as *mut u32).write_volatile(0); // SPI_MEM_C_MMU_ITEM_INDEX_REG
+                    (((0x5008C000 + 0x37c) as *const u32).read_volatile() & 0xff) << 16 // SPI_MEM_C_MMU_ITEM_CONTENT_REG
+                };
             } else if #[cfg(any(feature = "esp32c5", feature = "esp32c6", feature = "esp32c61", feature = "esp32h2"))] {
                 let paddr = unsafe {
                     ((0x60002000 + 0x380) as *mut u32).write_volatile(0);

esp-hal/CHANGELOG.md

@@ -12,6 +12,9 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - C5 and C61: Enable RTC timekeeping (#5449)
 - C61: usb-serial-jtag and debug-assist (#5427)
 - C61: dedicated gpio (#5426)
+- Initial ESP32-P4 (chip revision v3.0+) support (#5400)
+- P4: Initial peripheral support for GPIO, UART, I2C, SPI, DMA, USB Serial/JTAG, eFuse, SYSTIMER (#5400)
+- P4: AP-HEX PSRAM driver stub with configurable HP L2MEM cache/RAM split via `ESP_HAL_CONFIG_L2_CACHE_SIZE` (#5400)
 
 ### Changed
 

esp-hal/Cargo.toml

@@ -111,6 +111,10 @@ esp32c61 = { version = "0.3", features = ["critical-section", "rt"], optional =
 esp32h2 = { version = "0.19", features = ["critical-section", "rt"], optional = true }
 esp32s2 = { version = "0.31", features = ["critical-section", "rt"], optional = true }
 esp32s3 = { version = "0.35", features = ["critical-section", "rt"], optional = true }
+# ESP32-P4 PAC: use git rev fc3e6d4 (matching firmware consumers) -- the
+# crates.io release of esp32p4 0.2 doesn't match this revision's generated
+# register layout, so we intentionally stick with the git dep here.
+esp32p4 = { version = "0.2", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "fc3e6d4" }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
 riscv            = { version = "0.15.0" }
@@ -154,6 +158,7 @@ rt = [
     "esp32c2?/rt",
     "esp32c3?/rt",
     "esp32c6?/rt",
+    "esp32p4?/rt",
     "esp32h2?/rt",
     "esp32s2?/rt",
     "esp32s3?/rt",
@@ -231,6 +236,20 @@ esp32c6 = [
     "esp-sync/esp32c6",
     "esp-metadata-generated/esp32c6",
 ]
+## ESP32-P4 (chip revision v3.x / eco5 only, RISC-V dual-core HP + LP core)
+## NOTE: This targets P4X (ESP32-P4NRW16X/32X) with chip revision >= v3.0.
+## NRND variants (without X suffix) are NOT supported.
+## Based on TRM v0.5 (Pre-release) and Chip Revision v3.x User Guide v1.0.
+esp32p4 = [
+    "dep:esp32p4",
+    "esp-riscv-rt/rtc-ram",
+    "esp-riscv-rt/clic-48",
+    "procmacros/rtc-fast",
+    "procmacros/has-lp-core",
+    "esp-rom-sys/esp32p4",
+    "esp-sync/esp32p4",
+    "esp-metadata-generated/esp32p4",
+]
 ##
 esp32c61 = [
     "dep:esp32c61",