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walk-free B0: honest needs_legacy_walk=false on the 20 inert STM32 models#515

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perf/walk-free-b0-inert
Jul 11, 2026
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walk-free B0: honest needs_legacy_walk=false on the 20 inert STM32 models#515
w1ne merged 1 commit into
mainfrom
perf/walk-free-b0-inert

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@w1ne w1ne commented Jul 11, 2026

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Batch B0 of the walk-free campaign (plan: docs/walk-free-plan branch, PR #514). Mechanical, additive-only sweep: needs_legacy_walk() = false on the 20 STM32 models whose tick is verified structurally inert (trait-default no-op, no scheduler hooks): GpioPort, Lptim, Rcc, Pwr, Rng, Crc, Dac, Dbgmcu, Fmc, Quadspi, UsbOtg, Sdmmc, Comp, Tsc, Iwdg, Wwdg, Rtc, Sai, Nvic, and Flash (verified: H5 ops drain per-instruction via requires_cycle_accurate, not the walk — tick is no-op for all layouts).

Two plan corrections found and encoded:

  • scb's real ticking dev is installed by configure_cortex_m (descriptor path leaves an inert placeholder), and DWT is appended by configure_cortex_m with real CYCCNT tick work — so the campaign-surface test builds the runtime-faithful bus (from_config + configure_cortex_m), not from_config-only.
  • New pinned-surface test: with walk_deleted stripped, the walk-forcing set is exactly 22 ids (21 Class-B + dwt), listed on failure; and derive_walk_deletable() stays false — zero behavior change by construction.

All lanes green: workspace lib, jit+event-scheduler lib (1840 passed), invaders e2e 5/5 both lanes incl. the interval and derived-vs-explicit differentials, clippy -D warnings both lanes, fmt.

Batch B0 of the walk-free STM32 campaign (docs/walk_free_plan.md). Assert
needs_legacy_walk()==false on the 20 STM32 model types whose tick() is a
structural no-op in every state (pure register banks / stubs / lazy-read
models), so they no longer force the per-cycle legacy walk.

Each override verified against the model's tick path: none of these types
override tick()/tick_elapsed()/on_event()/sync_to()/uses_scheduler() — they
use the trait defaults and emit nothing from the walk. Flash is marked too:
its H5 erase/bank-swap ops drain via requires_cycle_accurate/drain_pending_op
per instruction, never the walk, so tick() is the default no-op for all
layouts. stub (syscfg) already carries the override.

Structures marked: GpioPort, Lptim, Rcc, Pwr, Flash, Rng, Crc, Dac, Dbgmcu,
Fmc, Quadspi, UsbOtg, Sdmmc, Comp, Tsc, Nvic, Iwdg, Wwdg, Rtc, Sai.

New unit test (bus::tick::walk_free_campaign) pins the campaign's remaining
walk-forcing surface on the runtime invaders bus (from_config +
configure_cortex_m, flag stripped): the exact Class-B set awaiting scheduler
migration plus the core DWT, and asserts derive_walk_deletable() stays false.
Zero behaviour change: Class B still forces the walk, so the invaders bus does
not flip walk-deletable.
@w1ne
w1ne merged commit d01a865 into main Jul 11, 2026
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@w1ne
w1ne deleted the perf/walk-free-b0-inert branch July 11, 2026 15:53
w1ne added a commit that referenced this pull request Jul 18, 2026
walk-free B0: honest needs_legacy_walk=false on the 20 inert STM32 models
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