This repository contains a Verilog implementation of a basic pipelined processor. The processor design divides instruction execution into multiple stages, allowing instructions to overlap in execution to improve overall performance and throughput compared to a non-pipelined processor.
This project is a hardware description of a pipelined CPU architecture, implemented entirely in Verilog. It serves as a learning tool for understanding the fundamentals of pipelined processor design, common hazards, and how to organize control logic for multiple pipeline stages.
- Implements instruction fetching, decoding, execution, memory access, and write-back stages in a pipeline.
- Improves CPU throughput by processing several instructions simultaneously at different stages.
- Handles basic pipeline control such as stalls or forwarding (if applicable based on code).
- Supports a basic instruction set architecture suitable for educational purposes or further development.
- Verilog source files of the pipeline stages and CPU modules
- Testbenches for simulation (if included)
- Supporting modules and utilities to demonstrate CPU operation
- Clone the repository: 'git clone https://github.com/vsntll/Pipelined-Processor.git'
- Use a Verilog simulation tool (e.g., ModelSim, Vivado, or similar) to compile the design and run simulations.
- Study the pipeline stages implementation and experiment by modifying or extending the design.