Virtual Memory & MMU Pipeline Simulator (C++ / Raylib)

A C++ operating systems and hardware architecture simulator that models the complete Memory Management Unit (MMU) virtual-to-physical address translation pipeline, including Translation Lookaside Buffer (TLB) caching, page table walks, dirty-page disk write-backs, and interactive Raylib visualization. It executes FIFO, LRU, and Optimal (Bélády's) page replacement algorithms side-by-side on the same address trace to compare page fault rates and Effective Access Time (EAT).

• Live API & Class Documentation: Doxygen Documentation

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Table of Contents

• Overview & Architecture
• Page Replacement Algorithms
• Repository File Structure
• Prerequisites & Build / Run Instructions
• Reproducible Configuration & Input Trace
• Performance Metrics & GUI Output
• License

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Overview & Architecture

This project simulates the complete virtual-to-physical memory translation hierarchy:

Component	Source Files	Function
TLB (Translation Lookaside Buffer)	TLB_table.h, TLB_table.cpp	Fast associative cache for recent Virtual Page Number (VPN) $\rightarrow$ Physical Frame translations ($1\text{ ns}$ lookup).
Page Table & Frame Manager	Page_frame.h, Page_frame.cpp	Full VPN $\rightarrow$ Physical Frame mapping with valid and dirty bit tracking ($10\text{ ns}$ miss penalty).
Physical RAM Simulation	Ram_memory.h, Ram_memory.cpp	Byte-addressable physical memory array storing active page frames.
Backing Store (Hard Disk)	HardDisk.txt (generated/read at runtime)	Persistent backing store for page-fault loads and dirty-page eviction write-backs ($1,000\text{ ns}$ penalty).
Interactive GUI Visualizer	mem_visualization.h/.cpp, Drawer.h/.cpp	Raylib graphical dashboard comparing FIFO, LRU, and Optimal hit/fault metrics and step-by-step frame allocations.

┌─────────────────────────────────────────────────────────┐
│                     Virtual Address                     │
│              ┌──────────────┬──────────┐                │
│              │     VPN      │  Offset  │                │
│              └──────┬───────┴─────┬────┘                │
│                     │             │                     │
│              ┌──────▼──────┐      │                     │
│              │     TLB     │      │                     │
│              │  (Cache)    │      │                     │
│              └──┬───────┬──┘      │                     │
│            Hit  │       │ Miss    │                     │
│              ┌──▼───────▼──┐      │                     │
│              │ Page Table  │      │                     │
│              │ (FIFO/LRU/  │      │                     │
│              │    OPT)     │      │                     │
│              └──────┬──────┘      │                     │
│                     │ Frame #     │                     │
│              ┌──────▼─────────────▼───┐                 │
│              │         RAM            │                 │
│              │  memory[frame][offset] │                 │
│              └──────────┬─────────────┘                 │
│                         │ Dirty eviction                │
│              ┌──────────▼─────────────┐                 │
│              │     HardDisk.txt       │                 │
│              │    (Backing Store)     │                 │
│              └────────────────────────┘                 │
└─────────────────────────────────────────────────────────┘

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Page Replacement Algorithms

The simulator executes three replacement strategies independently on the same address stream:

1. FIFO (First-In, First-Out)
   • Policy: Evicts the oldest resident page frame in physical memory using a queue (std::list).
   • Audit Log: Writes step-by-step frame transitions to FIFO_logging.txt.
2. LRU (Least Recently Used)
   • Policy: Evicts the page frame whose last reference is furthest in the past using an $O(1)$ hash map (std::unordered_map) coupled with a doubly linked list.
   • Audit Log: Writes eviction traces to log.txt.
3. OPT (Optimal / Bélády's Algorithm)
   • Policy: Pre-scans the future address trace buffer and evicts the page frame whose next reference is furthest in the future (establishing the theoretical lower bound on page faults).
   • Audit Log: Writes eviction traces to OPT_logging.

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Repository File Structure

Memory-Simulator-System/
├── OS_project.cpp                 # Main entry point; runs FIFO, LRU, and OPT and launches GUI
├── Virtual_Memory_manager.h/.cpp  # Orchestration logic for the three simulation modes
├── TLB_table.h/.cpp               # TLB cache lookup, replacement, and hit/miss counters
├── Page_frame.h/.cpp              # Page table translation, dirty-bit tracking, and disk I/O
├── Ram_memory.h/.cpp              # Physical memory frame array and Page_frame_node structs
├── FileConfiguration.h/.cpp       # JSON config parser and hexadecimal address stream reader
├── ADRESS_POP.h/.cpp              # Address stream preprocessing utilities
├── mem_visualization.h/.cpp       # Raylib GUI window and comparative chart controller
├── Drawer.h/.cpp                  # Frame table and metric rendering primitives
├── Parameters.json                # Simulation configuration parameters (frames, TLB size, latency)
├── OS_project.slnx / .vcxproj     # Visual Studio 2022 solution and project files
├── docs/                          # Generated Doxygen HTML/LaTeX documentation
└── LICENSE                        # MIT License

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Prerequisites & Build / Run Instructions

Option 1: Visual Studio 2022 (Windows — Recommended)

The project includes a Visual Studio 2022 solution (OS_project.slnx / OS_project.vcxproj) configured with NuGet (packages.config) for raylib.5.5.0:

1. Clone the repository:

   git clone https://github.com/usman-irshad1/Memory-Simulator-System.git
   cd Memory-Simulator-System

2. Open OS_project.slnx (or OS_project.vcxproj) in Visual Studio 2022.
3. Right-click the solution in Solution Explorer and select Restore NuGet Packages.
4. Ensure Parameters.json and an input trace file (addresses.txt) are present in the working directory, then press Ctrl + F5 to build and launch.

Option 2: Command-Line Compilation (g++ with Raylib)

g++ -std=c++17 -O2 OS_project.cpp Virtual_Memory_manager.cpp TLB_table.cpp Page_frame.cpp Ram_memory.cpp FileConfiguration.cpp ADRESS_POP.cpp mem_visualization.cpp Drawer.cpp -o MemorySimulator -lraylib -lopengl32 -lgdi32 -lwinmm
./MemorySimulator

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Reproducible Configuration & Input Trace

1. Checked-In Configuration (Parameters.json)

To reproduce the 4-page-frame GUI comparison screenshots shown below, Parameters.json is configured with 4 physical frames (physical_size: 4, page_size: 1) and a 4-entry TLB:

{
    "physical_size": 4,
    "page_size": 1,
    "TLB_size": 4,
    "virtual_size": 18446744073709551615,
    "latency": 10
}

(You can also scale physical_size to 40960 and page_size to 4096 to simulate 4 KB pages across 40 KB of RAM).

2. Input Address Trace Format (addresses.txt)

Create or edit addresses.txt in the project root with one hexadecimal virtual address and access mode (R for Read, W for Write) per line:

0x0001 R
0x0002 W
0x0003 R
0x0004 R
0x0001 R
0x0005 W
0x0002 R
0x0006 R
0x0003 W
0x0004 R

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Performance Metrics & GUI Output

The simulator computes Effective Access Time (EAT) across all requests:

$$\text{EAT} = \frac{(\text{Requests} \times 1\text{ ns}) + (\text{TLB Misses} \times 10\text{ ns}) + (\text{RAM Reads} \times \text{Latency}) + (\text{RAM Writes} \times \text{Latency} \times 2) + (\text{Dirty Evictions} \times 1000\text{ ns})}{\text{Total Requests}}$$

Comparative Summary View (4 Page Frames)

Step-by-Step Frame Allocation Views

• FIFO Replacement Trace:
• LRU Replacement Trace:
• Optimal (OPT) Replacement Trace:

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License

This project is distributed under the MIT License.