Computer Engineering | Digital IC & RISC-V Architecture (SystemVerilog) · Systems & Physics Simulation (C++17 / Java)
I am a Computer Engineering student focused on cycle-accurate RTL processor & FPGA accelerator design (SystemVerilog) and high-performance systems, physics, and OS simulation (C++17, C, Java), with applied coursework in speech and embedded machine learning (PyTorch, TinyML).
Seeking: Actively seeking Digital Design / FPGA / Computer Architecture (
RTL/RISC-V) and Systems / Embedded Software Engineering (C++/C) internships and entry-level roles. Reach me directly at usmanirshad2006@gmail.com.
| Project | Domain & Stack | Engineering Summary |
|---|---|---|
| RISC-V Processor Architecture (RV32I / RV32IM) | Computer Architecture · SystemVerilog · Verilog · Vivado |
32-bit FSM-controlled Multi-Cycle RV32IM processor (unified memory, hardware multiply/divide/remainder unit) and Single-Cycle RV32I core, accompanied by a 5-stage digital logic progression. |
| FPGA 3D CNN Hardware Accelerator | FPGA / RTL Design · SystemVerilog · Virtex-7 · Vivado |
Parameterized 3D convolution engine featuring 3 parallel 27-bit DSP MAC cores, a 3D Address Generation Unit (AGU), dual-port Block RAM streaming, and hardware ReLU activation. |
| simpec — 3D Urban Traffic & Signal Optimization Engine | Systems Simulation · C++17 · Raylib 3D · PyTorch · CMake |
Microscopic traffic simulator (IDM/MOBIL physics) with OpenStreetMap (.osm) geodetic projection, A*/Dijkstra dynamic rerouting, and Q-Learning/GA/ResNet signal optimization. |
| Virtual Memory & MMU Pipeline Simulator | OS Architecture · C++17 · Raylib · Live Docs |
Simulates virtual-to-physical address translation, associative TLB caching, page table walks, dirty-page disk write-backs, and FIFO/LRU/Optimal replacement with Effective Access Time (EAT) analysis. |
| Autonomous Drone Swarm Simulator | Control & Robotics · Java 21 · JavaFX 3D |
6-DOF rigid-body multi-UAV simulator featuring consensus-based formation control, artificial potential field collision avoidance, stochastic packet-loss modeling, and CSV telemetry. |
| Urdu Phoneme Recognition & GOP Pipeline | Speech ML · Python · PyTorch · Wav2Vec2 |
Fine-tuned IndicWav2Vec-Hindi CTC phoneme recognizer achieving 9.47% Test PER on Common Voice Urdu, paired with a 44-phoneme Urdu G2P engine and logit-based Goodness-of-Pronunciation (GOP) alignment. |
- Adaptive Highway Traffic Simulator (
v1.0CEP) (C++·Live Docs) — Earlier inter-city highway traffic simulator implementing BPR congestion weighting and Longest-Queue-First signal control. - Asynchronous Multithreaded Music Manager (
C++·SFML 3·Live Docs) — Thread-safe audio player backed by a custom templateDoublyLinkedList<T>and backgroundstd::threadtrack transitions. - TinyML Respiration / Humidity Spike Detector (
Python·ESP32 / Arduino) — Custom NumPy Logistic Regression classifier deployed as C++ firmware on a microcontroller with a DHT11 sensor. - Educational Huffman Coding Demo (
C++·Live Docs) — Demonstrates character frequency analysis, Huffman tree construction, and prefix-code tree reconstruction. - CS Practice Projects & Algorithms Archive (
C++·C·C#) — Coursework archive of 124+ foundational data structure, algorithm, and OOP practice implementations.
- Digital IC Design & Computer Architecture:
SystemVerilog·Verilog HDL·RISC-V ISA (RV32I/M)·FSM & Datapath Design·AMD/Xilinx Vivado·XSim Behavioral Verification - Systems & Simulation Programming:
C++ (C++17)·C·Java (JavaFX 3D)·Multithreading (std::thread, std::atomic)·CMake·Raylib·SFML - Applied Machine Learning & Edge AI:
Python·PyTorch·Wav2Vec2 / CTC Forced Alignment·TinyML (ESP32 / Arduino)·NumPy
- Email: usmanirshad2006@gmail.com
- GitHub: github.com/usman-irshad1