performance-power-area

RTL implementations of high-performance 64-Bit adder architectures, exploring carry computation, synthesis, timing analysis, and PPA trade-offs with post synthesis GLS with selected architectures taken to GDSII 🔢.

RTL implementations of high-performance 32-Bit multiplier architectures, exploring arithmetic datapaths, synthesis, timing analysis, PPA trade-offs with post-synthesis GLS and characterization of impact of carry-propagation architectures on multipliers performance. 🔢.