active-hdl

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Here are 5 public repositories matching this topic...

peterkaczorowski / freddie-simul

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Simulation of Atari Freddie chip functionality in Verilog

simulation vhdl atari gtkwave atari8bit active-hdl

Updated Nov 12, 2024
VHDL

MM-Robin / DI_projects

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VHDL lab projects — combinational adders, sequential counters & 7-segment display on CPLD | HAW Hamburg

simulation vhdl embedded-systems modelsim digital-circuits cpld hardware-design active-hdl

Updated May 15, 2026
VHDL

Holmes-99 / pipelined-risc-processor-verilog

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5-stage pipelined 32-bit predicated RISC processor designed and implemented in Verilog - includes datapath, control path, hazard handling, and testbench verification.

verilog hardware-designs computer-architecture logisim palestine risc-processor pipline predicate-logic birzeit-university encs active-hdl

Updated Apr 24, 2026
Verilog

Roozbehsn / VHDL-Multiplier-Algorithms

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Implementation of two digital multiplier algorithms in VHDL using Active-HDL: Array Multiplier and Add-and-Shift Multiplier. This repository compares different hardware multiplication techniques and their architectures.

vhd vhdl-code activehdl active-hdl

Updated Jul 30, 2026
VHDL

mohamed-12-tarek / Cryptographic-Coprocessor-Design

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A modular 16-bit cryptographic coprocessor implemented in VHDL with a custom ISA, verified using Active-HDL simulations and waveform analysis.

cryptography fpga processor vhdl embedded-systems computer-architecture digital-design hardware-accelerator hardware-design active-hdl cryptographic-coprocessor

Updated May 17, 2026
VHDL

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