6t-sram

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eshwarikollapudi / Design-Analysis-of-6T-SRAM-Cell

**Design & Analysis of 6T SRAM Cell** is a CMOS-based VLSI project that designs and evaluates a conventional 6T SRAM cell using Cadence Virtuoso and Spectre. The project analyzes read/write operations, transistor sizing, Voltage Transfer Characteristics (VTC), and Static Noise Margin (SNM) to optimize stability, speed, and power efficiency.

electronics sram vlsi cadence-virtuoso electronics-engineering vlsi-design electronics-projects 6t-sram

Updated Aug 2, 2026

Marut-777 / 6T-SRAM-LTspice

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Design, simulation and verification of a CMOS 6T SRAM cell in LTspice including Hold, Write, Read and Bit-line Capacitance analysis.

electronics memory spice sram vlsi semiconductor cmos ltspice analog-simulation 6t-sram

Updated Jul 7, 2026
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