[lionelZhaowy]

The EEPROM HAL does not request STOP on its final payload/read command. It can return when FIFO conditions are satisfied while the host is still finishing the transaction. The write path also lacks the device write-cycle wait.

Set the final STOP flags. Poll the actual DIF host status before controller reuse and before returning. For writes, read the RTC frequency through the current official register field. Reject zero before I2C MMIO. Request ceil(rtc_freq / 200) + 1 CLINT ticks after host idle, including one tick for RTC phase. The Microchip datasheet specifies a maximum 5 ms write cycle.

Keep block/device encoding and payload chunk progression separate. This branch preserves the old chunk helper. General writes larger than half the FIFO still need the independent chunk-progression fix.

Validation used official Cheshire 6c6dd5e834347f72c7be31cd6c41021ec293c5b9 and its locked actual I2C DIF cd3153de2783abd3d03d0595e6c4b32413c62f14. The host test executes the real HAL and DIF with the existing instrumented MMIO interface. FIFO/RX responses are ready while host idle is deliberately delayed by four status reads.

• Same six cases: one aligned one-byte read, zero-RTC write rejection, and aligned one-byte writes at RTC frequencies 1/200/32768/UINT32_MAX.
• Original: 25 command/order errors. Patch: zero errors.
• Check the final STOP flag, return after host idle, write-delay callback order and literal tick values, return code, data, and guards.
• GCC -std=gnu11 -O2 -Wall -Wextra -Werror: no warnings.

Public commands and test adapters are in sw/tests/host/EEPROM_COMPLETION.md. The RTC field maps to a typed host register object. The CLINT callback records delay requests rather than elapsed time. This checks software command/order behavior. It does not claim EEPROM/controller RTL or physical timing validation. No EEPROM model is included.

AI assistance: OpenAI Codex assisted implementation, test, and validation. A separate AI review checked the actual changes and results. This was not a human review.