Repository navigation

All pull requests

Labels (11)Milestones (1)New pull request

Open

(40)

Closed

(212)

[target/sim] Reset POSIX ELF loader state between files
#315lionelZhaowy opened Nov 7, 2026
Space VIP DMI writes for strict Capture status
#314lionelZhaowy opened Nov 7, 2026
Request EEPROM STOP and wait for host completion
#313lionelZhaowy opened Nov 7, 2026
Keep EEPROM chunks within the requested data range
#312lionelZhaowy opened Nov 7, 2026
Encode EEPROM block and chip-select bits in the control byte
#311lionelZhaowy opened Nov 7, 2026
Sample resolved I2C inputs while the VIP drives the bus
#310lionelZhaowy opened Nov 7, 2026
fix(idma_wrap): Connect backend busy to 1D frontend
#309sidcraftscode opened Nov 3, 2026
target/sim: Preserve leading bytes during unaligned ELF preload
#308lionelZhaowy opened Oct 26, 2026
Add Verilator support
#307ezelioli opened Oct 16, 2026Contributor
Bump CVA6 to pulp-v3 branch
#306ezelioli opened Oct 13, 2026Contributor
4
feat: bump debug module version and use ndmreset.
#303yvantor opened Oct 3, 2026Contributor
4
sw: Consume the iDMA register headers instead of regenerating them
#299DanielKellerM opened Sep 23, 2026
2
SoCDAML project "SystemRDL support for AXI VGA peripheral" adaptions for Cheshire
#293swueest opened Aug 19, 2026
1
CLIC: SystemRDL based register generation
#292ezelioli opened Aug 7, 2026Contributor
4
fix: derive the SPM addrmap size from the LLC config
#289DanielKellerM opened Aug 2, 2026
feat: parametrize Cheshire for 32-bit (XLEN) cores
#287Xeratec opened Jul 16, 2026Member
9
feat(smp): add software and vip support for multiple non-coherent cores
#277ricted98 opened Jun 17, 2026Contributor
4
chore(deps): bump python and github actions + setup dependabot
#276fischeti opened Jun 12, 2026Contributor
2
feat: Build dtb with bitstream
#275CyrilKoe opened May 27, 2026Contributor
feat(fpga): Add Alveo u280 fpga support
#271smanoni opened May 6, 2026Contributor
target/xilinx: Add VCU108 support
#264celuk opened Mar 30, 2026
treewide: Update CVA6 to pulp-v3, switch to HPDCache and pulp-linux
#259paulsc96 opened Feb 20, 2026Collaborator
mt/fesvr : Add FESVR support to cheshire
#248mtravaillard opened Oct 2, 2025
Add ZCU104 board support
#245AbdelkadirChantar opened Sep 4, 2025
[RVV] Add support for Ara vector processor
#231mp-17 opened Jun 24, 2025

Navigation Menu

Repository navigation

All pull requests

[target/sim] Reset POSIX ELF loader state between files

Space VIP DMI writes for strict Capture status

Request EEPROM STOP and wait for host completion

Keep EEPROM chunks within the requested data range

Encode EEPROM block and chip-select bits in the control byte

Sample resolved I2C inputs while the VIP drives the bus

fix(idma_wrap): Connect backend busy to 1D frontend

target/sim: Preserve leading bytes during unaligned ELF preload

Add Verilator support

Bump CVA6 to `pulp-v3` branch

feat: bump debug module version and use ndmreset.

sw: Consume the iDMA register headers instead of regenerating them

SoCDAML project "SystemRDL support for AXI VGA peripheral" adaptions for Cheshire

CLIC: SystemRDL based register generation

fix: derive the SPM addrmap size from the LLC config

feat: parametrize Cheshire for 32-bit (XLEN) cores

feat(smp): add software and vip support for multiple non-coherent cores

chore(deps): bump python and github actions + setup dependabot

feat: Build dtb with bitstream

feat(fpga): Add Alveo u280 fpga support

target/xilinx: Add VCU108 support

treewide: Update CVA6 to `pulp-v3`, switch to HPDCache and `pulp-linux`

mt/fesvr : Add FESVR support to cheshire

Add ZCU104 board support

[RVV] Add support for Ara vector processor

Pull requests