[lionelZhaowy]

The I2C input buffers in vip_cheshire_soc_tristate use the inverse DUT output enable. When the DUT drives SDA or SCL low, the corresponding input becomes high impedance. The controller then cannot observe the resolved line value.

Connect both I2C inputs directly to their resolved wires. Preserve the output buffers, pullups, and all SPI buffers.

Validation used official main 6c6dd5e834347f72c7be31cd6c41021ec293c5b9. The same finite 78-check test ran against both versions with VCS W-2024.09-SP1. It instantiated the complete real tristate module, extracted without edits. A package shim supplied only the SPI chip-select port width.

• Sweep all 16 combinations of DUT/peer low or release controls for SDA and SCL.
• Check both resolved wires and returned inputs, release transitions, and unchanged SPI input gating.
• Original: exactly 16 input mismatches, all z instead of 0, followed by the expected failure.
• Patch: 78 checks, zero errors, and a normal finish at 250 ns.
• Limits: 1 us HDL deadline and 60 seconds wall-clock per run.

The public test and commands are in target/sim/test/. No EEPROM model is needed. This verifies the simulation wrapper only. It does not claim full controller, EEPROM, or SoC verification. No synthesizable RTL changes.

AI assistance: OpenAI Codex assisted the patch, test, and validation. A separate AI review checked the actual source and logs. This was not a human review.