[Xeratec]

Adds an optional register cut on the DMA's AXI manager port, controlled by a new
DmaEnableAxiCut configuration bit.

Disabled by default (DmaEnableAxiCut : 0), which instantiates axi_cut with
Bypass = 1'b1 — a pure passthrough. No functional or timing change for any existing
configuration.

Changes

• cheshire_pkg: new bit DmaEnableAxiCut in the DMA parameter group, defaulted to 0
  in DefaultCfg.
• cheshire_idma_wrap: new EnableAxiCut parameter and an axi_cut between the iDMA
  backend and axi_mst_req_o/axi_mst_rsp_i, following the same
  .Bypass ( ~<cfg bit> ) idiom already used for the AMO post-cuts in cheshire_soc.
  The wrapper now also takes the individual axi_mst_*_chan_t types that axi_cut
  requires.
• cheshire_soc: forwards Cfg.DmaEnableAxiCut and the channel types to the wrapper.
• docs/um/arch.md: documents the new parameter in the iDMA table.

[creinwar]

LGTM, thanks!