DRAFT: Initial FDR stage modules

[enorman24]

Overview

Opening this PR so everyone can start reviewing the FDR frontend work.
Everything is lightly tested, so this is mainly for early feedback rather than anything close to final.

Modules

Decode

• Right now it just routes/packs metadata.
• I’ll update it once I've added more to the branch handler.

Meta_Fetch_Unit

• Pulls metadata from the metadata cache based on the PC.
• I reused the Vortex memory interface for now. The actual cache/memory isn’t instantiated here since I assumed that happens at a higher level.
• Since the FDR stage only has one CTA at a time (vs. Vortex having lots of warps), some of the memory interface fields are unused or hardcoded.

Bitstream_Fetch/Load

• Reuses the VX memory interface like meta fetch.

Valid_Check

• Missing some logic for now. I’m waiting until the CTA Status Table + branch handler exist so the behavior is clear.

fdr_top

• Current top-level for the FDR stage.

Interfaces

• cta_sched_if: between the scheduler and FDR
• fdr_if: between FDR and downstream stages

Packages

• frontend_pkg: structs used in the frontend and transitions. Might get merged into a more general package eventually.
• dice_pkg: small changes (CTA count, mask size) - these may not be necessary

Testing

• I used ModelSim for the early testbenches since I’m more used to that workflow. I’ll switch over to VCS/Verdi as things get more complete and the tests get more complex.
• For now, all the testbenches are simple auto-generated ones to check basic behavior.

Testbenches exist for:
-meta_fetch
-bitstream_fetch
-decode
-fdr_top

Next Steps

1. Implement the branch handler
2. Finish Valid_Check + improve Decode once the branch handler and CTA Status Table are in place
3. Add ability to flush FDR Stage if there is a misprediction
4. Build more complete testbenches and update the fdr_top testbench once the branch handler is working