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  1. aadithyamanoj/Mini_Dice aadithyamanoj/Mini_Dice Public

    SystemVerilog 5 1

  2. ARM-Based-5-Stage-Pipeline-CPU ARM-Based-5-Stage-Pipeline-CPU Public

    5 stage pipeline CPU with ARM instruction set

    SystemVerilog

  3. Register-File-Layout Register-File-Layout Public

    16x13 register file layout with decoder, DFF, and muxes

  4. EE344-Stock-Market-Predictor EE344-Stock-Market-Predictor Public

    Jupyter Notebook

  5. Snakes-and-Apples Snakes-and-Apples Public

    SystemVerilog