Yosys uhdm2rtlil synthesis - #5
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Adds syn/uhdm2rtlil/, a Yosys synthesis flow driven by the Surelog SystemVerilog
front end (uhdm2rtlil) alongside the existing Yosys-slang syn/ flow. Surelog
parses the design to UHDM and the uhdm2rtlil plugin imports it to RTLIL
(read_sv), so the full SystemVerilog the rp32 cores use is synthesisable through
Yosys.
The gate-level result is verified by co-simulation: the synthesized netlist is
run against the original RTL under Verilator, comparing outputs every cycle
(the methodology uhdm2rtlil uses for designs the native Verilog front end can't
parse). The complete Mouse simple SoC co-simulates with 0 mismatches over 6000
cycles.
- build.sh : synthesise a design through uhdm2rtlil, memory-preserving flow
(proc; flatten; memory_collect — NO opt_mem, which would mangle
the $readmemh boot image and map the RAM to ~500k FFs).
- cosim.sh : synth + Verilator co-sim (RTL vs gate netlist), prints COSIM PASS.
- cosim_tb.sv / cosim_main.cpp : side-by-side testbench + driver.
- boot.hex : tiny deterministic GPIO boot program for the SoC RAM.
- README.md : prerequisites (a built uhdm2rtlil, Verilator 5.x), usage, notes.
Point UHDM2RTLIL_ROOT at a built uhdm2rtlil checkout (defaults to ~/uhdm2rtlil).
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
The ISA-spec struct (riscv_isa_pkg) and the I-decoder struct (riscv_isa_i_pkg)
were unpacked, which the upstream comment already flagged as a TODO ("change
when Verilator supports unpacked structures"). Unpacked, they cannot be driven
as flat vectors through synthesis: the enum built on `logic [$bits(isa_spec_t)-1:0]`
truncates, and `dec_t` — taken as a PORT by the r5p_* modules — can't be mapped
onto a flat netlist port. Make both `packed` (and `dec_t.siz` a fixed-width
`logic signed [31:0]` rather than `integer`), which is required for the Yosys/UHDM
synthesis flow and resolves the degu core's nested decoder struct reads.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Adds a design catalog (designs.sh) covering the Mouse/Hamster/Degu cores and the Mouse/Degu SoCs, a build.sh that synthesises any of them, and run.sh which synthesises all and co-simulates the ones with a deterministic testbench, printing a status table. build.sh now passes -top to Surelog so hierarchical modules with unbound parameters (e.g. the TCB arbiter's unpacked-array `PRI`) are elaborated as instances, not standalone — this unblocks synthesis of the full SoCs. Verified today: mouse_soc_simple co-sim PASS (0/6000). The full SoCs and the degu/hamster cores synthesise but still have unresolved TCB interface-config / decoder-struct reads in the UHDM front end (documented in the README status table); those are the next front-end items. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
The full Mouse/Degu SoCs instantiate r5p_soc_memory; the plain r5p_soc_memory.sv is written for a different TCB API (reads interface localparams `sub.DAT`/`sub.MOD` that this TCB version doesn't expose — even Verilator can't elaborate it). The __gowin_inference variant uses the resolvable `sub.CFG.BUS.DAT` struct-parameter form (and byte-enable writes), matching how the FPGA flows build these SoCs, so the full SoCs synthesise through uhdm2rtlil. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Make the RTL-vs-uhdm2rtlil-netlist co-simulation harness design-parameterised so it serves any COSIM="yes" SoC whose top ports match cosim_tb.sv, instead of being hard-wired to mouse_soc_simple: - cosim_tb.sv: instantiate the RTL and gate tops via `TOP_RTL` / `TOP_GATE` macros (defaulted for standalone use); cosim.sh supplies them with +define+. The two SoC tops share the same clk/rst/gpio_o/gpio_e/gpio_i/uart port set. - cosim.sh: take a design name (default mouse_soc_simple), pull TOP and the RTL source list from designs.sh, synthesise the FLAT `*_gate` netlist and Verilate it against the RTL sources. - designs.sh: document why the full TCB-interface `mouse_soc` stays COSIM="no" — Verilator (5.048) cannot unroll tcb_lite_if's `for (genvar i=1; i<=CFG.HSK.DLY; i++)` delay-line loop (interface-parameter struct field it won't fold), so there is no independent RTL reference to co-simulate the interface SoC against. The discrete mouse_soc_simple stays cosim'd and green. mouse_soc_simple co-sim: 6000 cycles, 0 mismatches (unchanged). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Initial PR to add complete support for all Cores/SOCs for this advanced SV design suite. See README in the PR for details.
Design status
./run.shsynthesises every design and co-simulates the ones with adeterministic self-contained testbench:
mousemouse_soc_simplemouse_socsub.CFG.HSK.DLY,sub.MOD) are unresolved (front-end limitation); Verilator can't build the interface RTL either, so no co-simdegudegu_sochamsteridu_rdt.jmp.jmp)