esp-rs · bugadani · May 4, 2026 · May 4, 2026 · May 4, 2026 · May 5, 2026
diff --git a/.github/copilot-instructions.md b/.github/copilot-instructions.md
@@ -15,6 +15,7 @@ Bare-metal `no_std` Rust HAL for Espressif SoCs. MSRV: **1.88.0** (source: `MSRV
 | esp32c6 | RISC-V | `riscv32imac-unknown-none-elf` | `--toolchain stable` |
 | esp32c61 | RISC-V | `riscv32imac-unknown-none-elf` | `--toolchain stable` |
 | esp32h2 | RISC-V | `riscv32imac-unknown-none-elf` | `--toolchain stable` |
+| esp32p4 | RISC-V | `riscv32imafc-unknown-none-elf` | `--toolchain stable` |
 
 ## Commands
 

diff --git a/.github/workflows/api-baseline-check.yml b/.github/workflows/api-baseline-check.yml
@@ -48,7 +48,7 @@ jobs:
       - uses: dtolnay/rust-toolchain@v1
         if: env.SKIP_CI != 'true'
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: stable
           components: rust-src
 

diff --git a/.github/workflows/binary-size.yml b/.github/workflows/binary-size.yml
@@ -49,6 +49,9 @@ jobs:
             esp32c5|esp32c6|esp32c61|esp32h2)
               echo "rust-target=riscv32imac-unknown-none-elf" >> $GITHUB_OUTPUT
               ;;
+            esp32p4)
+              echo "rust-target=riscv32imafc-unknown-none-elf" >> $GITHUB_OUTPUT
+              ;;
             *)
               echo "Error: Unknown SoC: ${{ matrix.soc }}"
               exit 1

diff --git a/.github/workflows/ci-nightly.yml b/.github/workflows/ci-nightly.yml
@@ -33,14 +33,15 @@ jobs:
           "esp32c6",
           "esp32c61",
           "esp32h2",
+          "esp32p4",
         ]
     steps:
       - uses: actions/checkout@v6
 
       # Install the Rust nightly toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: nightly
           components: rust-src, clippy, rustfmt
 

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
@@ -77,7 +77,7 @@ jobs:
       - uses: dtolnay/rust-toolchain@v1
         if: env.SKIP_CI != 'true'
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: stable
           components: rust-src
 
@@ -108,6 +108,7 @@ jobs:
           cargo xcheck ci esp32c6 --toolchain stable --no-lint --no-docs
           cargo xcheck ci esp32c61 --toolchain stable --no-lint --no-docs
           cargo xcheck ci esp32h2 --toolchain stable --no-lint --no-docs
+          cargo xcheck ci esp32p4 --toolchain stable --no-lint --no-docs
 
   detect-extras-runner:
     needs: get-labels
@@ -166,13 +167,13 @@ jobs:
       # Install the Rust stable toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: stable
           components: rust-src
       # Install the Rust nightly toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: nightly
           components: rust-src
 
@@ -184,7 +185,7 @@ jobs:
       - name: Build RISC-V docs
         if: matrix.group == 'riscv'
         shell: bash
-        run: cargo xtask build documentation --chips esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2
+        run: cargo xtask build documentation --chips esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4
 
   # --------------------------------------------------------------------------
   # MSRV
@@ -223,7 +224,7 @@ jobs:
       - uses: dtolnay/rust-toolchain@v1
         if: env.SKIP_CI != 'true' && matrix.group == 'riscv'
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,x86_64-unknown-linux-gnu
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf,x86_64-unknown-linux-gnu
           toolchain: ${{ env.MSRV }}
           components: rust-src,clippy
 
@@ -235,7 +236,7 @@ jobs:
       - name: msrv RISC-V (esp-hal)
         if: env.SKIP_CI != 'true' && matrix.group == 'riscv'
         run: |
-          cargo xtask lint-packages --chips esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2 --toolchain ${{ env.MSRV }}
+          cargo xtask lint-packages --chips esp32c2,esp32c3,esp32c5,esp32c6,esp32c61,esp32h2,esp32p4 --toolchain ${{ env.MSRV }}
 
       - name: msrv Xtensa (esp-hal)
         if: env.SKIP_CI != 'true' && matrix.group == 'xtensa'

diff --git a/.github/workflows/dispatch.yml b/.github/workflows/dispatch.yml
@@ -603,7 +603,7 @@ jobs:
           fi
 
           # Known chips — everything matching these is a chip, first token is the example
-          KNOWN_CHIPS="esp32 esp32c2 esp32c3 esp32c5 esp32c6 esp32c61 esp32s2 esp32s3"
+          KNOWN_CHIPS="esp32 esp32c2 esp32c3 esp32c5 esp32c6 esp32c61 esp32s2 esp32s3 esp32p4"
 
           EXAMPLE_NAME=""
           CHIPS_JSON="["

diff --git a/.github/workflows/hil.yml b/.github/workflows/hil.yml
@@ -146,6 +146,10 @@ jobs:
             rust-target: riscv32imac-unknown-none-elf
             runner: esp32h2-usb
             host: armv7
+          - soc: esp32p4
+            rust-target: riscv32imafc-unknown-none-elf
+            runner: esp32p4
+            host: aarch64
           - soc: esp32
             rust-target: xtensa-esp32-none-elf
             runner: esp32-jtag
@@ -244,6 +248,10 @@ jobs:
             rust-target: riscv32imac-unknown-none-elf
             runner: esp32h2-usb
             host: armv7
+          - soc: esp32p4
+            rust-target: riscv32imafc-unknown-none-elf
+            runner: esp32p4
+            host: aarch64
           - soc: esp32
             rust-target: xtensa-esp32-none-elf
             runner: esp32-jtag
@@ -392,6 +400,10 @@ jobs:
             rust-target: riscv32imac-unknown-none-elf
             runner: esp32h2-usb
             host: armv7
+          - soc: esp32p4
+            rust-target: riscv32imafc-unknown-none-elf
+            runner: esp32p4
+            host: aarch64
           - soc: esp32
             rust-target: xtensa-esp32-none-elf
             runner: esp32-jtag
@@ -482,6 +494,10 @@ jobs:
             rust-target: riscv32imac-unknown-none-elf
             runner: esp32h2-usb
             host: armv7
+          - soc: esp32p4
+            rust-target: riscv32imafc-unknown-none-elf
+            runner: esp32p4
+            host: aarch64
           - soc: esp32
             rust-target: xtensa-esp32-none-elf
             runner: esp32-jtag

diff --git a/.github/workflows/pre-rel-check.yml b/.github/workflows/pre-rel-check.yml
@@ -30,14 +30,14 @@ jobs:
       # Install the Rust stable toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: stable
           components: rust-src
 
       # Install the Rust nightly toolchain for RISC-V devices:
       - uses: dtolnay/rust-toolchain@v1
         with:
-          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
+          target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
           toolchain: nightly
           components: rust-src
 
@@ -79,5 +79,8 @@ jobs:
           cargo xcheck ci esp32c61 --toolchain stable --steps=lp-examples,examples,qa-test,tests
           cargo xtask build examples --toolchain stable --package=compile-tests all --chip=esp32c61
 
+          cargo xcheck ci esp32p4 --toolchain stable --steps=lp-examples,examples,qa-test,tests
+          cargo xtask build examples --toolchain stable --package=compile-tests all --chip=esp32p4
+
           cargo xcheck ci esp32h2 --toolchain stable --steps=lp-examples,examples,qa-test,tests
           cargo xtask build examples --toolchain stable --package=compile-tests all --chip=esp32h2
diff --git a/esp-alloc/CHANGELOG.md b/esp-alloc/CHANGELOG.md
@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 ### Added
 
+- Support for ESP32-P4 (#5523)
 
 ### Changed
 

diff --git a/esp-alloc/Cargo.toml b/esp-alloc/Cargo.toml
@@ -120,6 +120,8 @@ esp32c61  = ["esp-sync/esp32c61"]
 ##
 esp32h2   = ["esp-sync/esp32h2"]
 ##
+esp32p4     = ["esp-sync/esp32p4"]
+##
 esp32     = ["esp-sync/esp32"]
 ##
 esp32s2   = ["esp-sync/esp32s2"]

diff --git a/esp-hal/CHANGELOG.md b/esp-hal/CHANGELOG.md
@@ -12,7 +12,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 - C5 and C61: Enable RTC timekeeping (#5449)
 - C61: usb-serial-jtag and debug-assist (#5427)
 - C61: dedicated gpio (#5426)
-- Initial ESP32-P4 (chip revision v3.0+) support (#5400)
+- Initial ESP32-P4 (chip revision v3.0+) support (#5400, #5523)
 - P4: Initial peripheral support for GPIO, UART, I2C, SPI, DMA, USB Serial/JTAG, eFuse, SYSTIMER (#5400)
 - P4: AP-HEX PSRAM driver stub with configurable HP L2MEM cache/RAM split via `ESP_HAL_CONFIG_L2_CACHE_SIZE` (#5400)
 - C5 and C61: I2S support (#5483)

diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml
@@ -111,10 +111,7 @@ esp32c61 = { version = "0.3", features = ["critical-section", "rt"], optional =
 esp32h2 = { version = "0.19", features = ["critical-section", "rt"], optional = true }
 esp32s2 = { version = "0.31", features = ["critical-section", "rt"], optional = true }
 esp32s3 = { version = "0.35", features = ["critical-section", "rt"], optional = true }
-# ESP32-P4 PAC: use git rev fc3e6d4 (matching firmware consumers) -- the
-# crates.io release of esp32p4 0.2 doesn't match this revision's generated
-# register layout, so we intentionally stick with the git dep here.
-esp32p4 = { version = "0.2", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "fc3e6d4" }
+esp32p4 = { version = "0.2", features = ["critical-section", "rt"], optional = true, git = "https://github.com/esp-rs/esp-pacs", rev = "c4a5792c462c32116eb4a367a37c2d167ae94a40" }
 
 [target.'cfg(target_arch = "riscv32")'.dependencies]
 riscv            = { version = "0.15.0" }
@@ -236,10 +233,7 @@ esp32c6 = [
     "esp-sync/esp32c6",
     "esp-metadata-generated/esp32c6",
 ]
-## ESP32-P4 (chip revision v3.x / eco5 only, RISC-V dual-core HP + LP core)
-## NOTE: This targets P4X (ESP32-P4NRW16X/32X) with chip revision >= v3.0.
-## NRND variants (without X suffix) are NOT supported.
-## Based on TRM v0.5 (Pre-release) and Chip Revision v3.x User Guide v1.0.
+## ESP32-P4 (chip revision >= v3.x)
 esp32p4 = [
     "dep:esp32p4",
     "esp-riscv-rt/rtc-ram",

diff --git a/esp-hal/README.md b/esp-hal/README.md
@@ -70,7 +70,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
 | Camera interface          | ❌    |          |          |          |          |           |          | ❌       | ❌       | ⚒️      |
 | DAC                       | ⚒️   |          |          |          |          |           |          |          | ⚒️      |          |
 | Dedicated GPIO            |       | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      |          | ⚒️      | ⚒️      |
-| DMA                       | ⚒️   | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ⚒️      | ⚒️      | ⚒️      |
+| DMA                       | ⚒️   | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ❌       | ⚒️      | ⚒️      |
 | DS                        |       |          | [❌][884] [^1] | [❌][884] [^1] | [❌][884] [^1] |           | [❌][884] [^1] | ❌       | [❌][884] [^1] | [❌][884] [^1] |
 | ECDSA                     |       |          |          | [❌][5444] [^1] |          | [❌][5444] [^1] | [❌][5444] [^1] | ❌       |          |          |
 | ECC                       |       | ⚒️      |          | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ❌       |          |          |
@@ -106,7 +106,7 @@ For help getting started with this HAL, please refer to [The Rust on ESP Book] a
 | SPI slave                 | ⚒️   | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ❌       | ⚒️      | ⚒️      |
 | SYSTIMER                  |       | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ⚒️      | ⚒️      | ⚒️      |
 | Temperature sensor        | ⚒️   | ⚒️      | ⚒️      | [❌][5153] [^1] | ⚒️      | [❌][5421] [^1] | ⚒️      | ❌       | ⚒️      | ⚒️      |
-| Timers                    | ⚒️   | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      |          | ⚒️      | ⚒️      |
+| Timers                    | ⚒️   | ⚒️      | ⚒️      | ⚒️      | ⚒️      | ⚒️       | ⚒️      | ⚒️      | ⚒️      | ⚒️      |
 | Touch                     | ⚒️   |          |          | [❌][5164] [^1] |          |           |          | ❌       | [❌][1905] [^1] | [❌][1905] [^1] |
 | TWAI / CAN / CANFD        | ⚒️   |          | ⚒️      | [❌][5163] [^1] | ⚒️      |           | ⚒️      | ❌       | ⚒️      | ⚒️      |
 | UART                      | ✔️   | ✔️      | ✔️      | ✔️      | ✔️      | ✔️       | ✔️      | ⚒️      | ✔️      | ✔️      |

diff --git a/esp-hal/ld/esp32h2/esp32h2.x b/esp-hal/ld/esp32h2/esp32h2.x
@@ -1,5 +1,5 @@
 /* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 and ESP32-H2 have
-   IDs 0-31, so we much define the handler for the one additional interrupt
+   IDs 0-31, so we must define the handler for the one additional interrupt
    ID: */
 PROVIDE(interrupt0 = DefaultHandler);
 

diff --git a/esp-hal/ld/esp32p4/esp32p4.x b/esp-hal/ld/esp32p4/esp32p4.x
@@ -1,33 +1,10 @@
-ENTRY(_start)
-
-PROVIDE(_stext = ORIGIN(ROTEXT));
 PROVIDE(_max_hart_id = 1);
 
-PROVIDE(UserSoft = DefaultHandler);
-PROVIDE(SupervisorSoft = DefaultHandler);
-PROVIDE(MachineSoft = DefaultHandler);
-PROVIDE(UserTimer = DefaultHandler);
-PROVIDE(SupervisorTimer = DefaultHandler);
-PROVIDE(MachineTimer = DefaultHandler);
-PROVIDE(UserExternal = DefaultHandler);
-PROVIDE(SupervisorExternal = DefaultHandler);
-PROVIDE(MachineExternal = DefaultHandler);
-
-PROVIDE(ExceptionHandler = DefaultExceptionHandler);
-
 /* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6,
-   ESP32-H2, and ESP32-P4 have IDs 0-31, so we much define the handler for the
+   ESP32-H2, and ESP32-P4 have IDs 0-31, so we must define the handler for the
    one additional interrupt ID: */
 PROVIDE(interrupt0 = DefaultHandler);
 
-/* Peripheral interrupt symbols are provided by the esp32p4 PAC's `device.x`,
-   which is included by `hal-defaults.x`. No need to list them here. */
-
-PROVIDE(__post_init = default_post_init);
-
-/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
-PROVIDE(_setup_interrupts = default_setup_interrupts);
-
 /* # Multi-processing hook function
    fn _mp_hook() -> bool;
    This function is called from all the harts and must return true only for one hart,
@@ -36,38 +13,24 @@ PROVIDE(_setup_interrupts = default_setup_interrupts);
 */
 PROVIDE(_mp_hook = default_mp_hook);
 
-/* # Start trap function override
-  By default uses the riscv crates default trap handler
-  but by providing the `_start_trap` symbol external crates can override.
-*/
-PROVIDE(_start_trap = _default_start_trap);
-
-/* Must be called __global_pointer$ for linker relaxations to work. */
-PROVIDE(__global_pointer$ = _data_start + 0x800);
-
-/* NOTE: .trap section is generated by build.rs in rwtext.x, not duplicated here. */
+SECTIONS {
+  /* Shared sections - ordering matters */
+  INCLUDE "rwtext.x"
+  INCLUDE "rwdata.x"
+  /* End of Shared sections */
+}
 
 SECTIONS {
   /**
    * Bootloader really wants to have separate segments for ROTEXT and RODATA
-   * It also needs to be located in a separate 64k flash segment.
+   * Thus, we need to force a gap here.
    */
   .text_gap (NOLOAD): {
-    . = ALIGN(0x10000) + 0x20;
+    . = . + 8;
+    . = ALIGN(4) + 0x20;
   } > ROM
 }
-INSERT BEFORE .rodata;
-
-/* Shared sections - ordering matters.
-   rwtext.x and rwdata.x contain bare section directives that need a SECTIONS context.
-   We wrap them in SECTIONS {} blocks. */
-SECTIONS {
-  INCLUDE "rwtext.x"
-}
-
-SECTIONS {
-  INCLUDE "rwdata.x"
-}
+INSERT BEFORE .text;
 
 INCLUDE "rodata.x"
 INCLUDE "text.x"
@@ -77,4 +40,4 @@ INCLUDE "metadata.x"
 INCLUDE "eh_frame.x"
 /* End of Shared sections */
 
-_dram_data_start = ORIGIN(RAM) + SIZEOF(.trap) + SIZEOF(.rwtext);
+_dram_data_start = ORIGIN(RAM) + SIZEOF(.trap) + SIZEOF(.rwtext);
diff --git a/esp-hal/ld/esp32p4/memory.x b/esp-hal/ld/esp32p4/memory.x
@@ -14,25 +14,26 @@
        3      "0KB"                            0 KB      0x4FF00000
 */
 
-MEMORY
-{
-    /* CONFIG 0 */
 #IF ESP_HAL_CONFIG_L2_CACHE_SIZE_512KB
-    RAM : ORIGIN = 0x4FF80000, LENGTH = 0x4FFAE000 - 0x4FF80000
+RESERVED_L2_CACHE = 0x80000;
 #ENDIF
-    /* CONFIG 1 */
+
 #IF ESP_HAL_CONFIG_L2_CACHE_SIZE_256KB
-    RAM : ORIGIN = 0x4FF40000, LENGTH = 0x4FFAE000 - 0x4FF40000
+RESERVED_L2_CACHE = 0x40000;
 #ENDIF
-    /* CONFIG 2 */
+
 #IF ESP_HAL_CONFIG_L2_CACHE_SIZE_128KB
-    RAM : ORIGIN = 0x4FF20000, LENGTH = 0x4FFAE000 - 0x4FF20000
+RESERVED_L2_CACHE = 0x20000;
 #ENDIF
-    /* CONFIG 3 */
+
 #IF ESP_HAL_CONFIG_L2_CACHE_SIZE_0KB
-    RAM : ORIGIN = 0x4FF00000, LENGTH = 0x4FFAE000 - 0x4FF00000
+RESERVED_L2_CACHE = 0;
 #ENDIF
 
+MEMORY
+{
+    RAM : ORIGIN = 0x4FF00000 + RESERVED_L2_CACHE, LENGTH = 0x4FFAE000 - RESERVED_L2_CACHE - 0x4FF00000
+
     /* External flash (XIP via cache); +0x20 skips the IDF app image header. */
     ROM : ORIGIN = 0x40000000 + 0x20, LENGTH = 0x400000 - 0x20
Original file line number	Diff line number	Diff line change
Expand Up		@@ -9,6 +9,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

		### Added

		- Support for ESP32-P4 (#5523)

		### Changed

Expand Down