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Rushikesh-Dandgawhal/README.md

Hi there, I'm Rushikesh Dandgawhal 👋

RTL Design Engineer | VLSI Enthusiast | Verilog HDL | FPGA Design

Electronics & Telecommunication Engineering graduate with hands-on experience in RTL Design, Digital Design, FPGA Development, and Functional Verification. Passionate about designing synthesizable hardware, implementing Finite State Machines (FSMs), and verifying digital systems using industry-standard EDA tools.

🚀 Technical Skills

RTL & Digital Design

  • Verilog HDL
  • RTL Design
  • Digital Design
  • Finite State Machines (FSM)
  • Combinational & Sequential Logic
  • Functional Verification

EDA Tools

  • ModelSim
  • Intel Quartus Prime
  • RTL Simulation
  • RTL Synthesis
  • RTL Viewer
  • Technology Map Analysis

Programming

  • Python
  • C++
  • MySQL

📚 Currently Learning

  • SystemVerilog
  • FPGA Design
  • ASIC Design Flow
  • Verification Methodologies

💼 Featured Projects

🔹 AHB-to-APB Bridge (Verilog HDL)

Designed and implemented a synthesizable AMBA AHB-to-APB Bridge using Verilog HDL. Verified the design through functional simulation and synthesized it using Intel Quartus Prime.

Key Highlights

  • AMBA AHB to APB Protocol Conversion
  • FSM-Based Controller
  • RTL Design & Functional Verification
  • ModelSim Simulation
  • Intel Quartus Prime Synthesis

🔗 Repository: https://github.com/Rushikesh-Dandgawhal/AHB-APB-Bridge

🔹 Digital Alarm Clock (Verilog HDL)

Designed and implemented a modular Digital Alarm Clock using Verilog HDL featuring an FSM-based controller for time setting, alarm configuration, clock operation, and alarm triggering.

Key Highlights

  • Modular RTL Architecture
  • FSM-Based Alarm Controller
  • Timing Generator
  • Alarm Register
  • Key Register
  • Display Driver
  • Functional Verification
  • Intel Quartus Prime Synthesis

🔗 Repository: https://github.com/Rushikesh-Dandgawhal/Alarm_Clock

🔹 UART 16550A (SystemVerilog)

Designed and implemented a modular UART 16550A-style controller in SystemVerilog with TX/RX datapaths, FIFOs, baud-rate generation, programmable UART registers, interrupt handling, modem-control logic, and simulation-based verification.

Key Highlights

  • UART TX/RX Design
  • TX and RX FIFO Integration
  • Baud-Rate Generation
  • UART Register Interface
  • Parity and Framing Error Detection
  • Interrupt Generation and Priority Handling
  • Modem Status and Control
  • ModelSim Simulation
  • Intel Quartus Prime Synthesis

🔗 Repository: https://github.com/Rushikesh-Dandgawhal/UART-16550A

🎓 Internship

VLSI Design Internship – Maven Silicon

Hands-on Experience

  • RTL Design
  • Verilog HDL
  • Digital Design
  • Functional Simulation
  • Intel Quartus Prime
  • ModelSim
  • Basics of ASIC Design Flow

🎯 Career Interests

  • RTL Design Engineer
  • FPGA Design Engineer
  • ASIC Design Engineer
  • Verification Engineer
  • Digital Design Engineer

📫 Connect With Me

LinkedIn https://www.linkedin.com/in/rushikesh-dandgawhal/

GitHub https://github.com/Rushikesh-Dandgawhal

⭐ Always learning, building, and exploring Digital Design, RTL Development, FPGA Design, and ASIC Verification.

Popular repositories Loading

  1. AHB-APB-Bridge AHB-APB-Bridge Public

    RTL Design and Verification of an AHB to APB Bridge using Verilog HDL

    Verilog 1

  2. Alarm_Clock Alarm_Clock Public

    Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

    Verilog 1

  3. UART_Controller UART_Controller Public

    Synthesizable UART Controller using Verilog HDL with TX/RX, baud-rate generation, functional verification, and FPGA synthesis.

    SystemVerilog 1

  4. UART-16550A UART-16550A Public

    Synthesizable UART 16550A controller in SystemVerilog with TX/RX, FIFOs, baud-rate generation, register interface, interrupt control, modem control, simulation-based verification, and FPGA synthesis.

    SystemVerilog 1

  5. Rushikesh-Dandgawhal Rushikesh-Dandgawhal Public

    RTL Design | VLSI Engineer | Verilog HDL | SystemVerilog | FPGA | Digital Design

  6. Verilog-RTL-Projects Verilog-RTL-Projects Public

    A collection of RTL Design and Verification projects implemented in Verilog HDL with simulation waveforms, testbenches, and documentation.

    Verilog