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KietLe11 wants to merge 14 commits into
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top-init
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Top init#3
KietLe11 wants to merge 14 commits into
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top-init

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@KietLe11

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- Wired primary components (CCU, HSU, PAU, Mem, TR) for ML-KEM accelerator.

Current integration status:
- Unit error signals tied to 0 (units currently missing status exports).
- HSU coordinates/params (row, col, cbd_n) tied to 0.
- PAU operation mapped from CCU job descriptor.
- Verified top-level wiring and port mapping.
- Added "WARNING POINTS" documentation to module header.
@KietLe11 KietLe11 self-assigned this Apr 24, 2026
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📊 Hardware Synthesis Metrics

Target Top: qrem_core

Metric Target Value
Logic FPGA (Xilinx LUTs) 21058 LUTs
Memory FPGA (18K BRAMs) 12 Blocks
Area ASIC (CMOS2) N/A GEs
Timing Critical Path 93 Logic Levels

Generated automatically by the centralized Yosys + Slang CI Pipeline.

@QREM-CORE QREM-CORE deleted a comment from github-actions Bot Apr 24, 2026
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📊 Hardware Synthesis Metrics

Target Top: qrem_core

Metric Target Value
Logic FPGA (Xilinx LUTs) 21159 LUTs
Memory FPGA (18K BRAMs) 12 Blocks
Area ASIC (CMOS2) N/A GEs
Timing Critical Path 86 Logic Levels

Generated automatically by the centralized Yosys + Slang CI Pipeline.

@github-actions

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📊 Hardware Synthesis Metrics

Target Top: qrem_core

Metric Target Value
Logic FPGA (Xilinx LUTs) 21159 LUTs
Memory FPGA (18K BRAMs) 12 Blocks
Area ASIC (CMOS2) N/A GEs
Timing Critical Path 86 Logic Levels

Generated automatically by the centralized Yosys + Slang CI Pipeline.

@github-actions

github-actions Bot commented Jun 5, 2026

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📊 Hardware Synthesis Metrics

Target Top: qrem_core

Metric Target Value
Logic FPGA (Xilinx LUTs) 21969 LUTs
Memory FPGA (18K BRAMs) 12 Blocks
Area ASIC (CMOS2) N/A GEs
Timing Critical Path 76 Logic Levels

Generated automatically by the centralized Yosys + Slang CI Pipeline.

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2 participants