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QREM-CORE/keccak-fips202-sv
QREM-CORE/keccak-fips202-sv PublicA FIPS 202 compliant SystemVerilog implementation of the Keccak permutation (SHA-3/SHAKE). Features a high-frequency multi-cycle architecture, runtime-configurable modes (SHA3-256/512, SHAKE128/256…
SystemVerilog 1
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IEEEYorkU/ascon-sp800-232-sv
IEEEYorkU/ascon-sp800-232-sv PublicSystemVerilog hardware accelerator for the Ascon cryptographic suite, as specified in NIST SP 800-232. Optimized for Lightweight Cryptography (LWC), this implementation targets the 320-bit permutat…
SystemVerilog 6
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QREM-CORE/hash-sampler-unit
QREM-CORE/hash-sampler-unit PublicA unified hardware accelerator for QREM ML-KEM hashing and sampling, tightly coupling Keccak cores with polynomial samplers to minimize memory overhead and latency.
SystemVerilog
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quardinlyttle/RV32I-Hazard-Optimized-Core
quardinlyttle/RV32I-Hazard-Optimized-Core PublicOptimized RV32I processor with a 5-stage bypassed pipeline, hardware hazard mitigation, and same-cycle register file forwarding.
Makefile 1
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