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1 change: 1 addition & 0 deletions .github/actions/build-dramsim/action.yml
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,7 @@ runs:
if [ ! -d "DRAMsim3" ]; then
cp -r /nfs/home/share/gem5_ci/DRAMsim3 .
fi
rm -rf DRAMsim3/build
cd DRAMsim3 && mkdir -p build
cd build
cmake ..
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3 changes: 3 additions & 0 deletions configs/common/CacheConfig.py
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,9 @@ def _get_cache_opts(cpu, level, options):
prefetcher_attr = '{}_hwp_type'.format(level)
if hasattr(options, prefetcher_attr) and (not options.no_pf):
opts['prefetcher'] = create_prefetcher(cpu, level, options)
if level == 'l1i' and getattr(options, prefetcher_attr) == \
'FetchDirectedPrefetcher':
opts['demand_mshr_reserve'] = 2

return opts

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7 changes: 6 additions & 1 deletion configs/common/PrefetcherConfig.py
Original file line number Diff line number Diff line change
Expand Up @@ -29,7 +29,12 @@ def create_prefetcher(cpu, cache_level, options):
return NULL

if cpu != NULL:
prefetcher.registerTLB(cpu.mmu.dtb, cpu.mmu.functional)
prefetcher.registerTLB(
cpu.mmu.itb if cache_level == 'l1i' else cpu.mmu.dtb,
cpu.mmu.functional)

if prefetcher_name == 'FetchDirectedPrefetcher':
prefetcher.cpu = cpu

if prefetcher_name == 'XSCompositePrefetcher':
if options.l1d_enable_spp:
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2 changes: 2 additions & 0 deletions configs/example/kmhv3.py
Original file line number Diff line number Diff line change
Expand Up @@ -176,6 +176,8 @@ def setKmhV3Params(args, system):

# Enable prefetch buffers for all hardware prefetchers in this config.
args.enable_pf_buffer = True
if not args.no_pf and args.l1i_hwp_type is None:
args.l1i_hwp_type = 'FetchDirectedPrefetcher'

# Set default bp_type based on ideal_kmhv3 flag
# If user didn't specify bp_type, set default based on ideal_kmhv3
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16 changes: 16 additions & 0 deletions src/cpu/o3/BaseO3CPU.py
Original file line number Diff line number Diff line change
Expand Up @@ -255,6 +255,22 @@ def support_take_over(cls):

store_prefetch_train = Param.Bool(True, "Training store prefetcher with store addresses")

fdip = Param.Bool(False, "Enable fetch-directed instruction prefetch")
fdipLookaheadTargets = Param.Unsigned(
4, "Number of future FSQ targets to scan for FDIP")
fdipMaxPrefetchesPerCycle = Param.Unsigned(
2, "Maximum FDIP prefetch requests generated per cycle")
fdipMaxBlocksPerTarget = Param.Unsigned(
1, "Maximum cache blocks to prefetch for each FDIP target")
fdipMinTargetDistance = Param.Unsigned(
1, "Minimum distance from the current fetch target to prefetch")
fdipMinTargetAgeCycles = Param.Unsigned(
0, "Minimum predicted-target age before FDIP prefetches it")
fdipSkipTargetStartBlock = Param.Bool(
False, "Skip the first cache block of each FDIP target")
fdipMaxPendingTranslations = Param.Unsigned(
32, "Maximum FDIP translations in flight")

# value predictor
valuePred = Param.ValuePredictor(NULL, "valuepred unit")
enableSelectiveVPFlush = Param.Bool(False,
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6 changes: 6 additions & 0 deletions src/cpu/o3/cpu.cc
Original file line number Diff line number Diff line change
Expand Up @@ -340,6 +340,12 @@ CPU::regProbePoints()
ppDataAccessComplete = new ProbePointArg<
std::pair<DynInstPtr, PacketPtr>>(
getProbeManager(), "DataAccessComplete");
ppFTQInsert =
new ProbePointArg<branch_prediction::btb_pred::FdipFetchTargetPtr>(
getProbeManager(), "FTQInsert");
ppFTQRemove =
new ProbePointArg<branch_prediction::btb_pred::FdipFetchTargetPtr>(
getProbeManager(), "FTQRemove");

fetch.regProbePoints();
rename.regProbePoints();
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5 changes: 5 additions & 0 deletions src/cpu/o3/cpu.hh
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,7 @@
#include "cpu/o3/rob.hh"
#include "cpu/o3/scoreboard.hh"
#include "cpu/o3/thread_state.hh"
#include "cpu/pred/btb/fdip_target.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
#include "cpu/valuepred/valuepred_unit.hh"
Expand Down Expand Up @@ -193,6 +194,10 @@ class CPU : public BaseCPU

ProbePointArg<PacketPtr> *ppInstAccessComplete;
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;
ProbePointArg<branch_prediction::btb_pred::FdipFetchTargetPtr>
*ppFTQInsert;
ProbePointArg<branch_prediction::btb_pred::FdipFetchTargetPtr>
*ppFTQRemove;

/** Register probe points. */
void regProbePoints() override;
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