Yield-Aware CMOS Inverter Layout Design and Defect Analysis Using KLayout

Overview

This project demonstrates the design of a CMOS inverter using KLayout and the analysis of common semiconductor manufacturing defects affecting yield and functionality.

Layers Used

• N-Well
• Active (Diffusion)
• Polysilicon
• Contact
• Metal1

Defects Analyzed

1. Missing Contact Defect
2. Metal Open Defect
3. Metal Short Defect
4. Spacing Violation Defect
5. Poly Gate Break Defect

Files

• CMOS_INV_GOOD.gds
• CMOS_INV_GOOD.png
• Defect screenshots
• Project Report

Skills Demonstrated

• CMOS Layout Design
• KLayout
• Semiconductor Fabrication
• Yield Engineering
• Failure Analysis
• Defect Characterization