A hardware implementation of a UART transceiver in SystemVerilog, developed for the EN2111 Electronic Circuit Design module at the Department of Electronic and Telecommunication Engineering, University of Moratuwa.
A complete UART communication link was implemented and tested between two Altera DE2-115 FPGA boards. Binary values are transmitted from one board over UART and displayed on the 7-segment display of the receiving board, demonstrating successful end-to-end hardware communication.
- UART Transmitter: Serializes parallel data for transmission
- UART Receiver: Deserializes incoming bits and reconstructs data
- 7-Segment Display Driver: Displays received binary values on the DE2-115 onboard display
- Testbenches: Unit testbench for the transmitter and an integrated transmitter-receiver testbench
- rtl/ # SystemVerilog RTL source files
- transmitter.sv # UART transmitter module
- receiver.sv # UART receiver module
- uart.sv # Top-level transceiver module
- binary_to_7seg.sv # 7-segment display decoder
- simulation/ # ModelSim simulation files
- output_files/ # Quartus compilation outputs
| Item | Details |
|---|---|
| HDL | SystemVerilog |
| FPGA | Altera DE2-115 (Cyclone IV) |
| Synthesis | Intel Quartus Prime |
| Simulation | ModelSim |
Testbenches are provided for unit-level transmitter verification (transmitter_tb.sv) and integrated transmitter-receiver verification (trans_rec_tb.sv). Run using ModelSim.