RTL / FPGA Design Engineer at Thakshana Technologies, Sri Lanka.
I design VHDL-based DSP and modulation pipelines for FPGA-based satellite communication systems, targeting Xilinx UltraScale+ and Zynq platforms. My work spans timing closure, clock domain crossing resolution, SDR board bring-up, and embedded Linux integration.
I also teach a RISC-V and SystemVerilog course through SkillSurf at the University of Moratuwa.
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pipelined-mac-asic-study — Fixed-point MAC accelerator targeting 500 MHz in the Sky130 PDK. Full RTL-to-GDS ASIC flow (synthesis, CTS, P&R, post-PnR STA) with timing analysis and architectural learnings documented as an engineering investigation.
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FYP-18-RISCV-Core — Quad-core cache-coherent out-of-order RV64IMA processor with TAGE branch prediction, AXI-ACE interconnect, and shared L2 cache. Validated on Xilinx VCU118 at 40 MHz with near-linear benchmark scaling (3.92x on quad-core). Built as a final-year project at the University of Moratuwa.
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100line-processor — Compact RV32I RISC-V processor in SystemVerilog, built as a teaching reference for the SkillSurf computer architecture course.
VHDL · SystemVerilog · Verilog · Chisel · Vivado · Verilator · Sky130 · LibreLane · PetaLinux · C/C++ · Python
B.Sc. Engineering (Hons), Electronic & Telecommunication Engineering — University of Moratuwa (First Class, CGPA 3.91/4.0). Previously interned at Paraqum Technologies, working on floating-point extensions for a RISC-V processor in a SiFive-aligned verification workflow.