[Core] Generalize H3 SM70 execution and weight residency

[yangzhuxinyzx]

Purpose

H3's residual sharding rejected original floating weights, Ref2VA and every
adapter, while fused FP16 input preparation only recognized an INT8 method.
This change routes preparation through execution capabilities and supports
original FP16/W8A16 projections, active LoRA and opt-in TP2/TP4 residual sharding.
FP32 residuals and outputs, row-scale restoration and adapter addition before
TP reduction are preserved. TP1 keeps ordinary execution.

The shared SM70 GEMM/preparation module is independent of the H3 model package.
Original floating projections can explicitly select column-major storage with
--fp16-weight-layout column; the default is row-major. Original weight loading
rejects FP16 overflow instead of silently producing non-finite parameters.

Integration base: 4f19ef7a20db60bb0685e599bd3f4dd156202eed (onecat/main).
Implementation checkpoints: 1031bb70cf, 9623a9adb2. Duplicate-work check found no open H3
PR after the prior FA/FI/workflow/export changes were merged. This is the common
execution portion of the broader H3 >80 useful TFLOP/s/card campaign.

Test Plan

• GPU: prepared/normal LoRA equality, signed W8A16, original FP16, wide-range
  activation scaling, column-major/cuBLASLt, graph replay and non-H3 shapes.
• Distributed: compare repeated blocks on TP2/TP4, both native attention
  backends, original/INT8 adapted projections, padding and FP32 residuals
  larger than 65504. Run each distributed module in a separate torchrun.
• CPU: configuration, adapter loaders/schedules, FP16 overflow and FP32
  preservation, API and media export regressions.
• Full-model: matched mainline/candidate 720p five-second four-step generation,
  then the remaining workflow/precision/adapter quality and performance matrix.

Test Result

Using Python 3.12 and Torch 2.10.0+cu128 on V100 SXM2 32GB:

python -m pytest -q tests/video/test_h3_prepared_linear.py tests/video/test_h3_activation.py tests/video/test_h3_column_major.py
  28 passed in the GPU batch (24 GPU + 4 CPU layout checks; before the additional conversion checks)
torchrun --standalone --nproc-per-node=2 -m pytest -q tests/video/test_h3_residual_parallel.py -k test_gpu
  1 composite case passed on each of 2 ranks
torchrun --standalone --nproc-per-node=4 -m pytest -q tests/video/test_h3_residual_parallel.py -k test_gpu
  1 composite case passed on each of 4 ranks
CUDA_VISIBLE_DEVICES='' python -m pytest -q tests/video/test_h3_residual_parallel.py tests/video/test_h3_lora.py tests/video/test_h3_flashgen.py tests/video/test_h3_fasth3.py tests/video/test_h3_service.py tests/video/test_h3_prepared_linear.py -k 'not test_gpu'
  133 passed, 1 skipped, 8 deselected

Commands used the owned .venv/bin/python, native exclusive GPU leases,
task-built SM70 binaries and task-specific caches. Ruff and all commit hooks,
including mypy, passed. Raw commands, environments, binary hashes and logs:
/data/minimax-h3/sm70-general-20260909/; campaign status is retained in
docs/design/minimax_h3/GENERAL_SM70.md.

Prepared LoRA matches normal execution bitwise in the GPU operator tests.
The complete 720p/four-step control without residual sharding also matches
mainline video/audio latents bitwise, pre-encoding video SSIM is 1.0 and every
audio numerical gate passes.

The initial reduce-scatter residual path failed full quality: video/audio
latent relative L2 0.2957225/0.0565235, video PSNR 28.312 dB, SSIM 0.878025.
Its 62.624739 s / 50.009271 TFLOP/s/card result is rejected; the same-contract
post-warmup mainline baseline is 66.206537 s / 47.303750 TFLOP/s/card.

The fix preserves the replicated path's full FP32 all-reduce before selecting
local residual rows. It gives up the unqualified communication saving. The TP4
block oracle now passes bitwise on every TP2/TP4 rank (including both backends
and adapted original/INT8 blocks). Complete four-step validation of the fixed
residual path also passes: video/audio latents match frozen mainline bitwise,
all 124 pre-encoding frames match with SSIM 1.0, and all audio numerical gates
pass. This was a no-warmup quality control, not a performance comparison.
Original BF16 checkpoint through FP16/FP32 runtime, with LightX2V4 v1.2,
column layout and exact residual sharding also completes the 720p five-second
control: video/audio latents match frozen original-weight mainline bitwise,
all 124 decoded frames match (SSIM 1.0), audio spectral cosine is effectively 1
and RMS ratio is 1. See original-column-quality.json.

Both original-weight controls used pageable CPU masters: all-pinned startup
exhausted the 188 GiB host before denoise. The native deployment now exposes
--disable-host-weight-pinning / host_weight_pin_memory=False for all four
components. Additional tests: 43 config/VAE/workflow/API checks and two real
pinned/pageable alias-preserving transfer tests pass. The complete controls
used an artifact-local equivalent before this native flag was added. A later native-flag TP4 run at 324f246 also enables explicit shared VAE host storage and passes full latent/RGB/PCM comparison bitwise. Default pinning remains unchanged.

No >80 or formal three-run result is claimed. Original controls had no warmup
(69.044838 s ordinary vs 66.426983 s candidate), so no speedup is claimed.
Preservation against frozen mainline does not establish independent official
algorithm quality or human audiovisual acceptance.

The explicit --share-host-vae-weights --disable-host-weight-pinning policy shares checked immutable VAE CPU storage between this engine's TP workers. Layouts, mixed-dtype aliases, strides and offsets are preserved; private mappings isolate accidental writes, and the parent removes its owned tmpfs directory after workers stop. CPU coverage passes 19 checks and GPU storage roundtrips pass three load/offload cycles. Full original-weight Light4 generation at 1280x736/124 internal frames preserves final video/audio latents, all RGB frames and decoded PCM bitwise (shared-host-quality.json). Mapped physical PSS is 11,020,886,016 bytes versus four replicas (44,083,544,064 summed RSS), with zero private mapped pages at startup; owned cleanup succeeds. The single captured cold request is 66.365689 seconds denoise and 126.846697 seconds overall, not a warmed speed result. See SHARED_HOST_WEIGHTS.md.

The stacked accounting branch excludes duplicate column-LoRA A work; earlier throughput numbers above use the historical numerator and are not directly comparable to corrected results. The combined kernel branch currently measures 51.939 useful TFLOP/s/card, still below 80.

The explicit --weight-offload layer capacity policy stages disjoint DiT and encoder blocks from the existing host snapshot. Outer/shared storage and first-block normalization/AdaLN cache-probe consumers remain resident. Hooks release storage on success/failure and preserve column layouts, aliases and adapter buffers. Whole-component staging remains the default; fixed FP16 cache lists are incompatible with layer mode. CPU coverage passes 35 checks and GPU FP16/FP32 ownership/alias/tail tests pass three cycles. A complete TP1 original-weight Light4 request at 256x448/22 frames peaks at 15,473,571,328 bytes. Pageable and pinned masters produce bitwise-equal final latents, RGB and PCM; cold denoise is 126.274887/53.840319 seconds and request latency 152.031041/67.370839 seconds. These establish capacity and residency parity, not primary performance or independent official quality. Boundary timing includes async waits; offload discards GPU copies and performs no D2H weight transfer. See LAYER_WEIGHT_OFFLOAD.md.

Original FP16 projection conversion was independently scanned for all 208 attention/MLP matrices in each partition: no overflow/nonfinite values, aggregate relative L2 about 9e-10 with 4055/4058 tiny underflows. Protected FP32 tensors are excluded from conversion. All eight official Turbo artifacts are downloaded and hash/header verified; GPU coverage remains a separate gate.

Remaining gates

Keep this PR Draft. Remaining original-weight/Ref2VA/adapter generations, three-run
performance, full audiovisual review and AUTO qualification remain pending.
VSA, cross-step caches and subsequent attention-kernel optimization are separate
campaign changes. Active LoRA still gathers its unrotated input in the residual
path; the prepared row projections and explicit dual-basis column interface are
implemented, but adapter gather optimization remains work.

AI assistance: implementation and initial validation were performed with
OpenAI Codex. Human line-by-line review and independent validation remain
required before promotion from Draft.

Complete TP2 original-weight Light4 capacity/sharding check: whole-component DiT loading exceeds 32 GB/card and fails before denoise. Layer mode completes at 256x448/22 frames with 15,449,646,080 allocated bytes/card. Matched layer-mode ordinary/sharded residual controls reproduce final video/audio latents, all RGB and PCM bitwise (layer-tp2-quality.json). Captured cold denoise is 166.482792/90.431030 seconds, affected by host paging; no warmed speed comparison or primary-shape acceptance is claimed.