platform: disable custom all-reduce on SM70 (Volta) — TP2 was hitting non-converging capture + Xid 62 - #431
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On TP > 1 with 2x Tesla V100 32GB (SM70, PCIe, no NVLink), the custom all-reduce path leads to: - piecewise CUDA-graph capture that never converges (>45 min stuck at 0/3 graphs; ~3 min total once the custom all-reduce is disabled) - decode throughput collapse (50.5 -> 0.1 tok/s on a 27B AWQ model) - Xid 62 raised on BOTH GPUs, leaving nvidia-smi and the worker processes in D-state; the host requires a reboot to recover Returning False from use_custom_allreduce() for Volta makes the existing parallel-config fallback (NCCL) kick in automatically, which is stable for hours under the same workload. This mirrors the well-known guidance to pass --disable-custom-all-reduce on V100, but applies it at the platform level so users cannot miss it. Validated on 2x V100-SXM2-32GB, Qwen3.8-27B AWQ, TP2, max-model-len 262144: with the fix the engine starts, captures CUDA graphs in ~3 minutes and sustains 4-way concurrency for the full benchmark plan without any driver events. Signed-off-by: Joker <joker@sabatech.dev>
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Hardware validation of the mechanism (2x V100, TP2, 1.3.0 wheel, no CLI flag): We validated the exact mechanism this PR wires up by forcing the platform hook to return False at runtime (monkeypatching
This mirrors what the platform-level fix achieves natively for every Volta user. A full source build of the current main (1.5.0-RC state) is compiling in our lab; we will follow up if anything differs there. |
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Good question — yes. Our main-branch tests ran on a tree at So #262 fixes the VMM-safety crash of the custom all-reduce allocator, but the deeper incompatibility on SM70 TP2 (capture convergence + decode stability) remains — consistent with the README guidance that the custom all-reduce is unsupported on this architecture. That's why we think the platform-level default (this PR) is the right call, with #262 remaining valuable for architectures where the custom path is supported. |
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We tried a short TP2 reproduction on 2x V100 PCIe using a recent 1.5.0-dev runtime with #262 included, Qwen3.8-27B AWQ, and Custom AR enabled. PIECEWISE capture completed 3/3 in about 85 seconds, with no Xid and zero corrected/uncorrected ECC counters, so we could not reproduce the reported 0/3 hang or Xid 62. Could you check whether either GPU showed ECC counter changes, retired pages, or earlier Xid 48/63/64 events? It may also be useful to see whether the failure follows the same physical GPU when changing the TP2 pair. |
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Thanks @Leonccaa — this is very useful, and it changes the picture significantly. We checked the hardware history you asked about, and our box has a known-marginal secondary GPU: ECC / Xid evidence:
What this means for our report: with your clean 3/3-in-85s repro on healthy hardware — same model (Qwen3.8-27B AWQ), same tree including #262, Custom AR enabled — our failure cannot be attributed cleanly to the custom all-reduce on SM70. Our box's secondary GPU is a plausible confound (or co-factor), and we retract the claim of a general SM70 TP2 incompatibility. On this PR: we'd like to re-scope rather than withdraw, and defer to you on which fits upstream best:
We can also do the physical GPU-swap test you suggested in a maintenance window, but given the card is already RMA-bound, the clean replacement test seems more valuable. |
I've had a similar issue crop up a few months ago with one of my V100-16GBs that would sporadically fall off the bus under any load that touches NVLink. That specific GPU kept wanting to clock at 1200MHz, and only recently found the "fix" was downclocking to a conservative 1050 MHz with |
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Thanks for the data point @e-c-k-e-r — that matches our hardware picture (marginal V100 silicon destabilizing under load; ours is PCIe without NVLink but same class of symptom, and we also run conservative power caps at 275 W). A clock cap via |
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最新 main 审计发现当前 head 与 #435 相同，实际只有 cuda.py 的 7 行全 SM70 custom-allreduce 禁用，并非局部拓扑修复。当前 main 已有经验证的 V100 TP4 push collectives 和算子通信路线，此全局关停会一并移除既有加速。现有 TP2 故障证据不足以证明所有 SM70 拓扑均不支持；需要定位故障形状、拓扑和图捕获入口再作局部修复。保持 Open，本轮不合入全局性能回退。 |
4 participants
Summary
CudaPlatform.use_custom_allreduce()returned True unconditionally, so TP>1 onV100 (SM70) silently took the custom all-reduce path even though it is
unsupported on this architecture (already noted in the README known-issues).
This PR returns False for Volta (capability 7.0-7.4) so the existing
parallel-config fallback to NCCL kicks in automatically with the standard
debug message — users no longer need to know they must pass
--disable-custom-all-reduce.Evidence (2x Tesla V100-SXM2-32GB, PCIe, TP2, Qwen3.8-27B AWQ, 262K ctx)
Detailed timeline in issue #430.
Why this is not duplicating an existing PR
Searched issues/PRs for
custom all-reduce SM70: the closest are #262 (graph-captureVMM-safety of the custom AR — orthogonal) and #299 (TP4 small-AR tuning — different
path). No PR wires the platform hook for Volta; today only the manual flag or the
undocumented hook exist.
Tests run
prompts up to ~108K tokens), multiple hours: 0 Xid, clean dmesg, stable decode.
(
Disabled the custom all-reduce kernel because it is not supported on current platform.)python -m py_compile vllm/platforms/cuda.pypasses; change is 7 lines gated tocapability 7.0-7.4, other architectures unaffected.
AI assistance disclosure
This change was prepared with AI coding assistance (OpenCode agent, SabaTech.dev
lab). The submitting human reviewed every line, reproduced the failure and the fix
on real hardware, and takes accountability for the change.