[Kernel][SM70] Reduce DFlash2 FP8 verification below 20 ms

[yangzhuxinyzx]

Purpose

Reduce the official Qwen3.8-27B-FP8 + DFlash2 TP4 V100 complete speculative round from the frozen 21.899 ms baseline to strictly below 20.000 ms without changing verification semantics, output-quality scores, or acceptance beyond the existing -0.05 gate.

Base SHA: 62ad1e02693f4c857f3b7547cef1860ee54e8053.

The frozen trace attributes 9.549 ms of the 16.705 ms target phase to block-FP8 QPN8 projections. Work starts with exact M=8 operator races and only promotes candidates that win real-weight cold/warm CUDA Graph trials.

Test Plan

• Real-checkpoint M=8 QPN8 operator race for all five target shapes.
• Dequantized-FP32 numerical oracle and repeated CUDA Graph replay checks.
• Same-source TP4 FULL-Graph phase trace at the 1K production contract.
• Paired acceptance and scored quality/tool/structured-output gates before default enablement.

Test Result

• Baseline trace complete: 21.899004 ms complete round; 16.705168 ms target verify.
• Candidate results pending.

Large raw profiles remain outside Git under /data/minimax-h3/task-cache/v100-dflash2-fp8-verify-20260828/.