[Bugfix] Use FP32 state and E4M3 defaults for DFlash2

[yangzhuxinyzx]

Purpose

Make the SM70 DFlash2 E4M3 target use FP32 attention state consistently. Previously, q8 verification selected the legacy grouped kernel first and rounded normalized partial outputs to FP16; the scalar fallback also stored FP16 partials. The repaired grouped path could therefore be present and enabled without controlling DFlash2 arithmetic.

This change removes that E4M3 bypass, adds FP32 scalar partial storage/reduction, routes DFlash2 target q1 away from half-partial XQA, and admits 1728/3456 pages to the repaired grouped entry. --kv-cache-dtype fp8 now resolves to E4M3 on SM70 Flash-V100. The existing Qwen3.8 DFlash2 configuration enables FP32 logits by default. Explicit E5M2 and unrelated non-DFlash XQA routes remain available.

KV storage remains FP8, Tensor Core operands/final activations remain FP16. Precision revision 4 and a matching extension rebuild are required. Older binaries cannot silently fall back to half-partial E4M3 scalar execution. MTP is not enabled.

Test Plan and Results

• Base: 56f534e672657a6c7599afd6c0dcb2e2c211b2e3 (onecat/main). CUDA 12.8.93/GCC12, Torch 2.10+cu128, V100-SXM2-32GB.
• Initial routing build: 420 focused tests passed. Final scalar/q1/routing/DFlash2/LM-head follow-up: 338 passed. Native/planner regression run: 102 passed; four new scalar cases initially had an invalid across-stream workspace-identity assertion, and all five scalar checks pass after correcting that test. TP4 model verification is queued for idle cards.
• Rebuilt q8/page3296 graph ABBA: 20 warmups, 25 ABBA blocks, same E4M3 bytes/scales/query and one native library. At 256K, relative L2 vs PyTorch FP32 decreases from 0.00033226 to 0.00020327, near the FP16 rounding floor. Latency increases from 0.9462 to 1.5206 ms. This is an intentional precision change, not a speedup or a model-quality claim.
• Tests cover changed/zero live row lengths under graph replay, relocated pages, KV scaling, q16/scalar fallback, stale native rejection, dtype-separated workspaces and explicit legacy dtype preservation. Full reproduction details are in docs/design/sm70_dflash2_fp32_defaults.md.
• Matched model checks use Qwen3.8-27B-FP8, DFlash2 q8, one identical reserved TP4 GPU group, E4M3, FP32 logits and no MTP. Both arms pin identical native dependencies. Acceptance uses request-level counter deltas. One preliminary startup was stopped to complete the scalar fix; the next startup failed before model loading because another task had occupied GPU0–3. Neither is a model quality result.

Review Scope

This does not duplicate #556 (Gemma normalization/state-audit work) or #405 (FP8 verifier performance experiments). It addresses attention precision dispatch, scalar partial dtype and runtime precision defaults. Existing numerical failures are not reclassified based on a lower aggregate L2.

Raw local artifacts are indexed under dflash2-e4m3-fp32-default-20260908; model weights and generated binaries are excluded from this PR. AI assistance: Codex. Human review is required before merging.

Merge status clarification

The maintainer explicitly requested merging this change after being informed that the full TP4 model A/B remains queued. The reviewed head is 50e5b5d2fc09f872be5401a9f5eb471c85104be6; its CI checks all pass. Operator and routing results above are complete, but model acceptance/throughput and the final queued memory-safety run are not being relabeled as passed. The same-card TP4 queue continues with at most four GPUs and no MTP. A matching Flash-V100 precision-revision-4 rebuild is required to use the new E4M3 scalar/grouped policy; this merge does not publish a wheel or change running services.