[Model][SM70] Support Qwen3.8 Flash Next with PLE offload - #338
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yangzhuxinyzx merged 5 commits intoAug 28, 2026
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Integrate the Qwen3.8 Flash Next model and PLE CPU offload work from vLLM PRs #53896 and #53899, then carry the validated 1Cat SM70 compatibility layer for FP16 activations, hybrid caches, NVFP4 emulation, and top-token sampling. The included TP4 smoke covers checkpoint loading, PLE offload, prompt prefill, and one autoregressive decode step on four V100 32GB GPUs. Co-authored-by: huanghaoyan.hhy <huanghaoyan.hhy@alibaba-inc.com> Co-authored-by: zjy0516 <riverclouds.zhu@qq.com> Assisted-by: OpenAI Codex Signed-off-by: Leonccaa <166551845+Leonccaa@users.noreply.github.com>
Match the 1Cat mRoPE, FP8 skip, short-conv metadata, and host-to-device helper signatures. Narrow optional FP8 test scales so the upstream pre-commit mypy matrix can validate the imported code. Assisted-by: OpenAI Codex Signed-off-by: Leonccaa <166551845+Leonccaa@users.noreply.github.com>
Widen the 1Cat hybrid state-shape protocol to the current vLLM shape union and document intentional Qwen4Exp overrides for the older 1Cat Qwen3Next and pipeline-parallel interfaces. Assisted-by: OpenAI Codex Signed-off-by: Leonccaa <166551845+Leonccaa@users.noreply.github.com>
Apply the pinned Ruff 0.14.0 formatter to the two PR-specific files that differ from the current 1Cat main formatting baseline. Assisted-by: OpenAI Codex Signed-off-by: Leonccaa <166551845+Leonccaa@users.noreply.github.com>
Use four warps for the single-split sparse QSA prefill profile on exact SM70 devices while preserving the existing launch choices everywhere else. Add a pure policy test for the original profile boundaries and the V100-specific branch. The corresponding four-V100 TP4 gate improved 1K and 4K prefill by 5.47x and 6.16x with matching deterministic first tokens. Assisted-by: OpenAI Codex Signed-off-by: Leonccaa <166551845+Leonccaa@users.noreply.github.com>
This was referenced Aug 27, 2026
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…atest-main-20260828-0327 [Core][SM70] Repair Qwen4Exp PLE integration from #338
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Purpose
Add the Qwen3.8-Flash-Next Qwen4Exp model path, PLE CPU offload, and the SM70 compatibility needed to load and execute it on the 1Cat V100 runtime.
This is not a duplicate of an existing 1Cat PR: open and closed 1Cat PRs were searched before submission and no equivalent Qwen4Exp or PLE change was found. It adapts the still-open upstream model PR vllm-project/vllm#53896 and PLE-offload PR vllm-project/vllm#53899 to the 1Cat SM70 runtime.
The scope is intentionally limited to the reusable runtime core:
The separate AWQ g32 metadata adapter and extended performance benchmark remain in the local integration PR Leonccaa#4 and are not part of this upstream PR.
Test Plan
Test Result
Real 4x V100 validation passed on this core tree:
Static validation on the final core tree:
CI baseline note: the all-files pre-commit workflow remains red on repository-wide baseline issues. The run after the SM70 QSA commit has the same failing hook set as the immediately preceding core-PR run: Ruff format, typos, clang-format, markdownlint, SPDX normalization, forbidden-import, and legacy
torch.cudachecks. Neither QSA file appears in the generated failure diff; file-level pre-commit passes locally. In the same GitHub run, Ruff check and all four Python 3.10-3.13 mypy hooks pass. Unrelated repository-wide rewrites remain intentionally excluded.SM70 QSA prefill tuning
Commit
533b7a2b9keeps the existing GB300 and non-SM70 launch profiles unchanged, but uses four warps for exact-SM70 single-split sparse QSA prefill (base_programs > 512). The 72 KiB-per-CTA shape permits only one resident CTA per V100 SM; two warps left that CTA severely under-occupied.Four-rank CUDA profiling attributed 86.43% of 1K prefill kernel time to
_qsa_sparse_paged_gqa_splitk_kernel. At the exact TP4 shape, changing only two to four warps reduced its median from 178.4207 ms to 11.3883 ms (15.67x) with elementwise-exact FP16 output.End-to-end TP4 V100 results with the same W4A16 Marlin checkpoint path and PLE CPU offload:
Both deterministic prompts retained their baseline first token. This is a focused performance/correctness gate rather than full quality acceptance. The pure launch-policy test covers all existing profile boundaries plus the SM70/non-SM70 split; 7/7 tests and all file-level pre-commit hooks pass.
NVFP4 on V100 is an emulation feasibility path, not a production recommendation. The intended production follow-up is activation-aware AWQ W4A16 g32 while keeping PLE on CPU.
This PR is Draft because the upstream vLLM source PRs are still open and because a human maintainer must review the AI-assisted port before it is marked ready.
AI assistance
OpenAI Codex assisted with the port, diagnostics, tests, and PR preparation. Leon must review the code and upstream delta before ready-for-review.
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