amd64/arm64: expand compression assembly support

[zhouguangyuan0718]

What changed

• Add amd64 NOTB translation for register and memory operands.
• Add arm64 LSRW, TST, BMI, and BPL translation.
• Add arm64 FLDPQ pair loads and VMOVI byte-vector constants.
• Model the flag effects of the raw ARM64 encodings emitted by reedsolomon for TST X0, X0 and 64-bit SUBS immediate instructions.
• Distinguish zero-argument function-like macros from object-like macros, so calls such as TEST_SRC() expand without leaving a trailing ().
• Honor FuncSig.Name as the emitted symbol for external declarations, calls, and tail calls.

Why

Optimized compression dependencies exposed missing Plan 9 assembly coverage in LLGo:

• Minio's github.com/dchest/siphash dependency uses NOTB R11.
• github.com/klauspost/compress/s2 uses arm64 LSRW, a multi-line zero-argument TEST_SRC() macro, and calls runtime.memmove while LLGo links libc memmove.
• github.com/klauspost/reedsolomon uses BMI, BPL, and TST; its generated SVE assembly also emits flag-writing TST and SUBS instructions through WORD directives.
• github.com/minio/crc64nvme uses FLDPQ to load two 128-bit FP/vector registers and VMOVI to initialize a byte vector.

Without these translations, LLGo rejects selected assembly instructions, loses the condition flags needed by later branches, generates an invalid macro-expanded branch target, or cannot express an external source symbol whose emitted name differs.

Semantics

• NOTB flips only the selected low byte and preserves upper register bits; its memory form loads, flips, and stores one byte. Flags are unchanged.
• LSRW performs a 32-bit logical right shift, masks register shift amounts to 0-31, and zero-extends the result to 64 bits.
• TST updates the ARM64 logical N/Z flags, while BMI and BPL branch on the negative flag and its inverse.
• FLDPQ performs two 128-bit loads and writes the vector slots aliased by its F register pair; VMOVI supports the B8 and B16 byte arrangements.
• Raw WORD handling remains permissive and only decodes the known reedsolomon flag-writing encodings; unrelated embedded opcodes are still ignored as before.
• Empty parameter lists remain distinguishable from object-like macros during preprocessing.
• A non-empty FuncSig.Name selects the emitted external symbol while signature lookup remains keyed by the resolved Plan 9 symbol.

Validation

• Added regression coverage for amd64 NOTB; arm64 LSRW, TST, BMI, BPL, FLDPQ, VMOVI, and raw flag-writing words; zero-argument function-like macro expansion; and external FuncSig.Name on amd64/arm64.
• go test ./... passes on the combined PR branch.
• LLGo completes forced full builds of github.com/klauspost/compress/s2, github.com/klauspost/reedsolomon, and github.com/minio/crc64nvme while using this local plan9asm checkout.

[codecov]

Codecov Report

❌ Patch coverage is 79.16667% with 35 lines in your changes missing coverage. Please review.

Files with missing lines	Patch %	Lines
arm64_lower_word.go	59.37%	7 Missing and 6 partials ⚠️
arm64_lower_arith.go	54.54%	7 Missing and 3 partials ⚠️
amd64_lower_arith.go	70.37%	5 Missing and 3 partials ⚠️
arm64_lower_vec.go	95.74%	1 Missing and 1 partial ⚠️
preprocess.go	87.50%	0 Missing and 1 partial ⚠️
translate.go	80.00%	1 Missing ⚠️

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