Flop flops based SRAM Generation

[JingqunZhang]

I want to generate only RTL files and synthesize them using a new technology.
When I run the following command: make Verilog CONFIG=GemminiRocketConfig TOP=ChipTop VLSI_TOP=Gemmini MACROCOMPILER_MODE="--mode synflops" ,it seems that the generated RTL files still use the default SRAM generator. How can I correctly use MACROCOMPILER_MODE="--mode synflops" to ensure that the generated RTL files work properly. Thanks!