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feat: specialized linear layout for decoupling capacitor partitions#50

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chengyixu wants to merge 3 commits intotscircuit:mainfrom
chengyixu:feat/decoupling-caps-linear-layout
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feat: specialized linear layout for decoupling capacitor partitions#50
chengyixu wants to merge 3 commits intotscircuit:mainfrom
chengyixu:feat/decoupling-caps-linear-layout

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/claim #15

Summary

  • Bypass PackSolver2 for decoupling cap partitions: When SingleInnerPartitionPackingSolver encounters a partition with partitionType === "decoupling_caps", it skips the general packing algorithm and uses a new createLinearDecouplingCapLayout() method instead
  • Clean horizontal row layout: Decoupling capacitors are arranged in a single horizontal line, sorted by chipId for deterministic ordering, with consistent spacing using decouplingCapsGap (falls back to chipGap)
  • Centered at origin: The row is centered at x=0, y=0 so it integrates cleanly with the partition packing phase

Changes

lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts

  • Added early return in _step() for decoupling_caps partition type
  • Added createLinearDecouplingCapLayout() private method that places caps in a clean horizontal row

tests/PackInnerPartitionsSolver/LinearDecouplingCapLayout.test.ts

  • 5 new tests covering:
    • Linear row layout with correct Y-alignment and gap spacing
    • Full pipeline integration
    • Centering around origin
    • Deterministic ordering (sorted by chipId)
    • Non-decoupling partitions still use PackSolver2

Why this works

The existing pipeline already identifies decoupling caps (IdentifyDecouplingCapsSolver) and creates separate partitions for them (ChipPartitionsSolver with partitionType: "decoupling_caps"). The problem was that PackSolver2 produces messy, overlapping layouts for groups of identically-sized 2-pin components. This PR adds a targeted override: when a partition is known to contain only decoupling caps, arrange them in a clean row instead.

Zero impact on non-decoupling partitions — the early return only fires for tagged partitions.

Test plan

  • All 5 new tests pass (bun test tests/PackInnerPartitionsSolver/LinearDecouplingCapLayout.test.ts)
  • All existing tests pass (22 pass, 1 skip; the 1 pre-existing error in IdentifyDecouplingCapsSolver06.test.ts is a dependency issue on main)
  • Formatting passes (bun run format:check)

When a partition is tagged as "decoupling_caps", bypass the general
PackSolver2 and instead arrange capacitors in a clean horizontal row
centered at the origin. Caps are sorted by chipId for deterministic
ordering and spaced evenly using decouplingCapsGap (falling back to
chipGap). This eliminates the messy overlapping layout that PackSolver2
produces for groups of same-sized decoupling capacitors.

/claim tscircuit#15

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
@vercel
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vercel bot commented Mar 26, 2026

@chengyixu is attempting to deploy a commit to the tscircuit Team on Vercel.

A member of the Team first needs to authorize it.

Wilson Xu and others added 2 commits March 27, 2026 02:43
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Move the InputProblem data from LayoutPipelineSolver06.page.tsx into a
separate .data.ts file. This prevents the test from transitively loading
the LayoutPipelineDebugger component (and its circuit-to-svg dependency)
which has a missing export in the current pinned version.

Fixes the pre-existing test failure on main (1 fail, 1 error -> 0 fail).
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