uvm-register-model

Here are 7 public repositories matching this topic...

rggen / rggen

Code generation tool for control and status registers

asic fpga vhdl eda rtl verilog csr systemverilog soc uvm ral axi amba apb register-descriptions wishbone-bus uvm-ral-model uvm-register-model wiki-documents

Updated Jul 16, 2026
Ruby

SystemRDL / PeakRDL

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Control and status register code generator toolchain

asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model

Updated Jul 14, 2026
Python

SystemRDL / PeakRDL-uvm

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Generate UVM register model from compiled SystemRDL input

asic fpga eda uvm registers uvm-ral-model uvm-register-model

Updated Nov 25, 2025
Python

rggen / rggen-sample-testbench

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vhdl verilog systemverilog uvm uvm-ral-model uvm-register-model

Updated Jul 15, 2026
VHDL

rggen / rggen-sv-ral

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UVM RAL class package for RgGen

systemverilog uvm ral uvm-ral-model uvm-register-model

Updated Jan 7, 2026
SystemVerilog

AlphaLyrae0 / UVM_RAL_DPI_C_Example

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Example of C/C++ register access with name through UVM RAL

verilog systemverilog uvm dpi-c uvm-ral-model uvm-register-model

Updated Mar 15, 2026
SystemVerilog

Khallil973 / uvm-ral-register-verification

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UVM-based register verification environment using explicit predictor

systemverilog uvm testbench predictor uvm-ral-model uvm-register-model uvm-verification uvm-testbench designverification

Updated Mar 9, 2026
SystemVerilog

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uvm-register-model

Here are 7 public repositories matching this topic...

rggen / rggen

SystemRDL / PeakRDL

SystemRDL / PeakRDL-uvm

rggen / rggen-sample-testbench

rggen / rggen-sv-ral

AlphaLyrae0 / UVM_RAL_DPI_C_Example

Khallil973 / uvm-ral-register-verification

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