terasic-de1

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A simple sram controller and test for the altera DE1 FPGA board

vhdl sram vhdl-modules altera-fpga vhdl-coursework sram-controller vhdl-sram altera-de1 terasic-de1

Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board

Verified 8-bit multicycle processor in VHDL with exhaustive GHDL testing and Terasic DE1 FPGA integration.

fpga processor vhdl embedded-systems computer-architecture ghdl digital-design cpu-design terasic-de1 cyclone-ii

Synthesizable 16-bit integer square-root core in VHDL with exhaustive verification and Terasic DE1 FPGA integration.

fpga vhdl ghdl integer-arithmetic digital-design terasic-de1 cyclone-ii

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