MODNET (MODify NETlist): VHDL/Verilog Fault Injection system
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Jun 27, 2021 - Python
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synplify-pro
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FM Radio receiver & stereo decoder in SystemVerilog. Fully pipelined architecture achieving 102.3 MHz timing closure on FPGA. Featured optimizations: 32-stage restoring divider, staged FIR adder trees, and 100% covered UVM environment.
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Mar 17, 2026 - SystemVerilog
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