silicon-layout

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aditi-mahindrakar / Calculator_VLSI

This project demonstrates a complete RTL-to-GDSII digital VLSI design flow. I designed a 4-bit Arithmetic Logic Unit (ALU) using Verilog HDL, verified its functionality through simulation, and implemented its physical layout on the SkyWater 130nm PDK using the OpenLane flow.

calculator waveform yosys vlsi-physical-design testbench-verification silicon-layout

Updated Aug 7, 2026
Verilog

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