riscv-vector

Here are 6 public repositories matching this topic...

simplex-micro / riscv-vector-primer

Read chapters directly from this repo - do not use GitHub Pages link.

open-hardware riscv computer-architecture instruction-set-architecture risc-v embedded-ai edge-ai rvv riscv-vector vector-processing matrix-acceleration

Updated Jul 25, 2026

Asmory / Asmory

Star

Assembly package registry with ISA-aware dependency and Variant resolution

Updated Oct 8, 2026
Python

K-avi / gemm-bench

Star

Portable GEMM microkernels evaluating AVX2, AVX-512, NEON and RVV via MIPPv2

hpc simd high-performance-computing avx2 vectorization avx512 gemm arm-neon dgemm micro-benchmarks firestorm rvv meteorlake cortex-a76 spacemit mipp zen4 riscv-vector

Updated Oct 26, 2026
C++

AAH20 / tensor-forge

Sponsor

Star

Bare-Metal Deep-Kernel Fused JIT & Memory Bandwidth Optimizer for Frontier AI Accelerators (Tenstorrent, Triton, CUDA, Apple Silicon).

cuda quantization compiler-optimization roofline-model kernel-fusion deep-learning-compiler flash-attention tenstorrent triton-kernels fp8-quantization riscv-vector apple-silicon-mlx logaddexp-overflow memory-bandwidth-optimization

Updated Oct 3, 2026
Python

qianfenaichou / cie2026-xinxinxiangrong-xiangshan-vdot

Star

香山昆明湖 V2 自定义向量指令 vdot.vv：单条指令完成 K=8 int8 点积并写回 32 位结果，含 Chisel RTL、NEMU 参考模型与 difftest 验证 / Custom RVV vdot.vv (SEW=8, LMUL=1, K=8) for XiangShan Kunminghu V2: Chisel RTL, NEMU model, difftest.

chisel riscv rtl computer-architecture hardware-acceleration nemu dot-product rvv int8-quantization xiangshan difftest riscv-vector vector-extension custom-instruction

Updated Nov 8, 2026
C

sebishogun / simd

Star

Hardware-accelerated whole-slice SIMD vector primitives for Go (AVX-512, AVX2, NEON, SVE2, RVV) — zero cgo, zero dependencies, 100% portable Go fallback.

go golang performance high-performance neon assembly x86-64 simd matrix-multiplication avx2 vectorization arm64 avx512 no-cgo vector-search sve2 cgo-free riscv-vector

Updated Aug 27, 2026
Assembly

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