rf-ic-design

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mayankish / RF-IC-RX-FRONT-END

Complete 2.4 GHz RF receiver front-end designed in Cadence Virtuoso (180 nm CMOS) — cascode LNA, Gilbert cell mixer, and Gm-C IF filter. Serving as the analog verification layer for a 64 subcarrier OFDM PHY baseband. Simulated in Spectre RF.

mixer spectre cadence-virtuoso ofdm cmos analog-design rf-receiver rfic lna analog-ic 180nm-technology spectre-rf rf-ic-design

Updated Jun 12, 2026
Python

mayankish / GFSK-MODULATION-ON-FPGA

Star

GFSK modem (BT=0.5, 125 kbps) implemented in SystemVerilog on Xilinx Artix-7 — full TX/RX signal chain with Gaussian FIR, NCO FM modulation, Gardner timing recovery, and live BER measurement over UART.

modem fpga-soc xilinx-fpga gfsk fpga-programming rf-ic-design

Updated Jun 4, 2026
SystemVerilog

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