A fully pipelined 5-stage RV32I processor implemented in SystemVerilog. This design models instruction-level parallelism with forwarding and hazard detection, and passes all RISCOF compliance tests for the RV32I base ISA.

RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

A fault-tolerant, pipelined RISC-V processor system implemented in Verilog, featuring Triple Modular Redundancy (TMR), SECDED memory protection, error injection, and robust recovery mechanisms. Designed for research, education, and prototyping of reliable digital systems.

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

A 5-Stage Pipelined RISC-V Processor designed and implemented on FPGA (Artix-7 Nexys A7). Supports RV32I instructions set (R, I, S, B, U, J types) with ALU, control unit, hazard detection, forwarding, and pipeline registers. Verified through simulation and hardware testing with optimized timing and 4× performance gain.

RISCape is a 5-stage pipelined RISC-V processor

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

Pipelined ARMv8 with hazard detection and forwarding - Computer Architecture course project - Computer Science @ FAMAF (UNC)

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

This project is a custom 32-bit pipelined RISC processor in Verilog, featuring a 5-stage pipeline, hazard detection, and data forwarding. It demonstrates core CPU concepts and is ideal for learning about pipelined processor design and simulation.

A ModelSim project that implements a MIPS pipelined CPU in Verilog, enhancing efficiency through pipelining based on single-cycle CPU concepts.

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.