Custom VLSI design of a Jitter-Based True Random Number Generator (TRNG) with dynamic selection bit reconfigurability in Cadence Virtuoso. Features dual-VCOs, NLFSR, and 6T SRAM cells.
sram vlsi cadence-virtuoso hardware-security analog-ic-design trng entropy-source vco spectre-simulation phase-jitter
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Updated
May 27, 2026 - Stata