ElemRV - End-to-end Open-Source RISC-V Microcontroller
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Aug 6, 2026 - Scala
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open-source-silicon
Here are 36 public repositories matching this topic...
Tiny tapeout gf180 ocd sram test for the gf0p3 shuttle
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Jun 18, 2026 - Verilog
Clean-room container for building RTL → GDSII: a slim, pinned open-source EDA toolchain (Yosys · Verilator · OpenROAD · Magic · KLayout · Netgen · ngspice + sky130/gf180 PDKs), built from scratch on GitHub Actions and published to GHCR.
docker magic asic container eda vlsi yosys semiconductor klayout netgen ngspice gdsii physical-design openroad sky130 chip-design gf180mcu open-source-silicon rtl-to-gdsii vyges
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Aug 5, 2026 - Dockerfile
This project implements a tetrahedral oscillator inspired by the paper “Analysis and Design of a Tetrahedral Oscillator” by Richelle L. Smith and Thomas H. Lee. The oscillator is built from coupled inverter pairs, and its operating frequency is tuned by adding capacitive loads to the internal nodes.
spice gds oscillator mixed-signal cmos custom-layout ngspice ring-oscillator lef sky130 xschem magic-vlsi analog-ic open-source-silicon tiny-tapeout
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May 7, 2026 - Python
VyBox Lite: One-click Codespaces environment for trying Vyges chip/IP development in your browser.
eda verilog systemverilog semiconductor cocotb browser-ide github-codespaces chip-design open-source-silicon vyges vyges-ip vybox vybox-lite
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Feb 20, 2026 - JavaScript
Open-source waveguide mode analysis software
python simulation eda photonics silicon-photonics waveguide photonic-mode-solver mode-solver mode-analysis photonic-circuit integrated-photonics open-source-silicon eigenmode-solver photonic-design
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May 12, 2026 - Python
NumPy → streaming ISP hardware (Verilog) compiler
fpga hls numpy image-processing rtl verilog isp switchboard high-level-synthesis image-signal-processor hardware-design open-source-silicon
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Aug 11, 2026 - Python
World's first open-source Vedic math (Urdhva Tiryagbhyam) hardware multiplier. 8×8 RTL, synthesized with Yosys on ARM64 Termux.
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May 20, 2026 - Verilog
Capless digitally-trimmable LDO for IHP SG13CMOS5L — Chipalooza Challenge #2 IP.
analog eda ldo power-management mixed-signal voltage-regulator openframe apache-2 open-source-silicon ihp-sg13g2 sg13cmos5l chipalooza
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Jul 23, 2026
A 12-track height standard cell library built in SKY130 PDK. It is made up of 12 combinational cells, which were designed using Magic VLSI Layout Tool and characterized using
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Aug 11, 2026 - Python
Closed measurement kernels: coherent single-tone spectral (SNR/SINAD/THD/SFDR) and AC transfer (gain, bandwidth, unity frequency, phase margin).
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Aug 11, 2026 - Rust
Reproducible Yosys synthesis distro — from-source, multi-arch (amd64+arm64).
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Jul 18, 2026 - Shell
Floorplan initialization over the OpenDB design database: die/core area, site-grid snapping, and rows
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Aug 12, 2026 - Rust
Reproducible builds of mainline OpenROAD — slim container + relocatable binary
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Aug 13, 2026 - Shell
Row cutting and physical-cell insertion over the OpenDB design database: tap cells, endcaps, corners
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Aug 12, 2026 - Rust
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