learning-verilog

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Here are 4 public repositories matching this topic...

hashirshoaeb / Verilog-Codes

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This repository is to help macOS and linux users who have just started learning verilog.

macos vscode assignment verilog getting-started vscode-plugin linux-users scansion lab-tasks learning-verilog

Updated Jan 14, 2020
Verilog

mcleber / Verilog_Traffic_Light_Controller

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First steps with the Sipeed Tang Primer 20k FPGA.

verilog verilog-hdl gowin sipeed learning-verilog sipeed-tang-primer gowin-eda

Updated Mar 4, 2026
Verilog

mcleber / Verilog_7-Segment_Display_Controller_with_DIP_Switches

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This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.

display verilog bcd verilog-hdl 7 gowin sipeed learning-verilog sipeed-tang-primer gowin-eda

Updated Mar 4, 2026
Verilog

mcleber / Verilog_Testbench_Essentials

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A testbench is a special Verilog module used only for simulation.

verilog testbenches testbench verilog-hdl learning-verilog verilog-testbenches

Updated Mar 3, 2026
Verilog

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learning-verilog

Here are 4 public repositories matching this topic...

hashirshoaeb / Verilog-Codes

mcleber / Verilog_Traffic_Light_Controller

mcleber / Verilog_7-Segment_Display_Controller_with_DIP_Switches

mcleber / Verilog_Testbench_Essentials

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