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A digital clock system implemented with VHDL via Intel Quartus Prime and ModelSim.
Configurable real time clock on the Terasic DE0-CV board, using VHDL and custom ASM code
32-bit processor simulation and implementation on a FPGA, using VHDL and Intel Quartus Prime software
Traffic Light System designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 100%
⚙️ Field-Programmable Gate Array (FPGA) MIPS microprocessor
SystemVerilog (RTL) AES-based Hash core with FSMD architecture. Features a C golden model for verification and optimization for Intel Cyclone V FPGAs.
Memory Initialization File
These are the files we woked on in the EE Lab, including our project, an FPGA platformer game.
⚙️ Field-Programmable Gate Array (FPGA) MIPS microprocessor
Yahtzee game designed in VHDL for Digital System Design Course in EPFL BA2 (IC Section) Grade: 88.89%
A 32-bit RISC-V (RV32I) softcore implemented in Verilog HDL with a multi-cycle microarchitecture. Features a custom FSM-driven control unit and modular datapath. Developed as a Scientific Initiation (PIVIC) project at UNIFEI.
A Verilog-based door security system designed and simulated in Intel Quartus, developed step-by-step using an FSM approach (state diagram, state table, HDL coding) and verified through waveform analysis.
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