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iitt
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QAM system over the AWGN channel
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May 9, 2023 - MATLAB
A cycle-accurate 32-bit RISC-V (RV32I) simulator in C++ featuring a 5-stage pipeline, dynamically configurable 2-level cache hierarchy, and a full Virtual Memory subsystem with a Data TLB and Two-Level Page Table
simulator pipeline cpp lab riscv virtual-memory computer-architecture hazard-detection lru-cache tlb page-tables rv32i cache-memory iitt iit-tirupati cs209p
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May 13, 2026 - C++
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