An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast
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Sep 8, 2026 - Python
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hardware-software-co-design
Here are 12 public repositories matching this topic...
A humble exploratory PoC for a hardware-native, optical timing-frozen control plane engine. Fuses inline CUDA PTX, RAII memory tunnels, and 4D JAX shard_map structures to investigate 0ns-overhead fault-tolerant routing for hyperscale distributed AI.
distributed-systems fault-tolerance zero-copy cuda high-performance-computing compiler-optimization interconnect silicon-photonics jax pytorch-extension xla custom-kernels hardware-software-co-design ahead-of-time-compilation ai-infrastructure llm-infrastructure deepseek-v4 ptx-assembly hlo-compiler
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Aug 9, 2026 - Python
An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.
toolchain c-plus-plus fpga compiler processor assembler verilog academic-project computer-architecture cpu-design rtl-design hardware-software-co-design custom-isa
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Aug 6, 2026 - Verilog
An open-source live telemetry and system modeling engine for generative AI. Track total system resource utilization in real time across storage, memory paths, and compute blocks to eliminate black-box execution failures and accelerate the development of next-generation AI and generative AI architectures.
memory-management gpu-computing computer-architecture cache-hierarchy hardware-software-co-design generative-ai llm-inference bottleneck-analysis system-telemetry
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Aug 4, 2026 - Rust
AI-assisted smart irrigation system combining ESP32 embedded hardware, multi-source power electronics, self-hosted cloud backend, MQTT communication, automation workflows, and context-aware decision logic validated in real-world operation.
docker nginx mqtt iot automation esp32 self-hosted embedded-systems power-electronics system-design edge-computing engineering-productivity n8n smart-agriculture hardware-software-co-design ai-integration
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Jan 23, 2026 - C++
A Geometry-driven 1D Linear Fusion Infrastructure PoC: Eliminating 3D Tokamak computation overheads by shifting to a 1D linear trajectory, featuring sub-10ns branchless silicon kernels, 0ns zero-copy C++ bridges, and asyncio macro-orchestration.
fpga high-performance-computing asyncio control-theory closed-loop-control kalman-filter fault-tolerant pybind11 nuclear-fusion digital-twin cplusplus20 zerocopy realtime-control hardware-software-co-design branchless-programming plasma-control homeostasis-engine
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Sep 5, 2026 - Python
A Geometry-driven 1D Linear Fusion Infrastructure PoC: Eliminating 3D Tokamak computation overheads by shifting to a 1D linear trajectory, featuring sub-10ns branchless silicon kernels, 0ns zero-copy C++ bridges, and asyncio macro-orchestration.
fpga hls embedded-systems high-performance-computing asyncio asynchronous-programming control-theory closed-loop-control kalman-filter fault-tolerant pybind11 smart-grid digital-twin cplusplus20 zerocopy realtime-control hardware-software-co-design branchless-programming vivado-xdc homeostasis-engine
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Sep 5, 2026 - Python
Comprehensive survey of CNN hardware acceleration across FPGA, ASIC, and VLSI implementations spanning five real-world domains. Presents unified benchmarks, cross-domain optimisation strategies, and key research challenges for efficient, low-power, real-time AI systems; manuscript under review.
asic fpga deep-learning vlsi hardware-software-co-design real-time-inference cnn-hardware-acceleration
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Apr 3, 2026
FPGA hardware acceleration projects using SystemVerilog, AXI, DMA, C drivers, pipelining, and parallel compute architectures.
python c fpga parallel-computing embedded-systems vivado systemverilog pipelining pynq hardware-acceleration dma digital-design axi axi-stream axi4-lite memory-mapped-io hardware-software-co-design
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Jun 30, 2026 - SystemVerilog
Academic project implementing GPS-based distance and angle calculation on the SAYAC embedded processor, with custom ISA instructions for hardware acceleration and performance analysis.
embedded-systems isa computer-architecture systemc risc-v performance-optimization processor-design embedded-processors sayac gps-navigation hardware-software-co-design custom-instructions
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Jul 27, 2026 - C++
A simple experiment applying compressible flow principles to soften distributed gradient communication stalls.
hpc zero-copy automatic-differentiation cuda high-performance-computing sharding low-level bare-metal backpropagation fluid-dynamics compiler-optimization monkey-patch distributed-training pytorch-extension xla mixture-of-experts hardware-software-co-design deepseek-v3 rocev2 dynamic-shapes
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Jul 24, 2026 - Python
Design and implementation of an ASIC with an 8051 microcontroller core. Includes VHDL modules, C applications, RTL simulations, and mixed-signal validation. Focused on hardware-software co-design and optimization.
vhdl embedded-systems logic-synthesis 8051-architecture asic-design hardware-software-co-design microcontroller-integration rtl-simulation mixed-signal-simulation digital-circuit-optimization
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Jan 8, 2025 - VHDL
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