edram

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shreyanshsharma639 / DMA-Memory-Subsystem

A high performance DMA subsystem using AXI4 Full protocols and a custom 16 bank eDRAM architecture. Designed for maximum throughput and minimal leakage, it features predictive bank wakeup logic and deterministic timing closure at 100MHz.

fpga rtl vivado dma system-design vlsi-design edram testbench-verification

Updated Mar 11, 2026
Verilog

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